---------------------------------------------------------------------------------------------------
-- TEST_BENCH_A7_XADC.VHD
-- (C) 2025 JAPAN LOGIC DESIGN 日本ロジック設計
-- No unauthorized reproduction or AI training allowed.
-- Unauthorized reproduction prohibited.
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
-- Ver : Date		: Description
-- 0.1 : 2026.02.10	: 1st Version
---------------------------------------------------------------------------------------------------
-- 解説:
--	[TOP_FPGA.VHD]用のテストベンチ
--	ModelSim, Vivadoシミュレーション で共有できる記述としてある
---------------------------------------------------------------------------------------------------

-- Use IEEE library -------------------------------------------------------------------------------
library	IEEE;
use		IEEE.STD_LOGIC_1164.ALL;
use		IEEE.STD_LOGIC_ARITH.ALL;
use		IEEE.STD_LOGIC_UNSIGNED.ALL;
use		IEEE.STD_LOGIC_MISC.ALL;

use		IEEE.std_logic_textio.all;
use		std.textio.all;

-- エンティティ宣言 -------------------------------------------------------------------------------

entity	TEST_BENCH is
end		TEST_BENCH;

architecture SIM of TEST_BENCH is -----------------------------------------------------------------

-- 固定値定義 -------------------------------------------------------------------------------------
constant	CYCLE12 : time := 83.3 ns;	-- クロック 12MHz

-- 信号定義 ---------------------------------------------------------------------------------------

-- タイトル用 -----------------------------------
	signal simulation_title1	: string( 1 to 20 );	-- 波形の上側に表示するタイトル
	signal simulation_title2	: string( 1 to 20 );
-- システム -------------------------------------
	signal CLK_IN				: std_logic;
	signal nRESET				: std_logic;
	signal SWITCH_RES_IN		: std_logic;
	signal SIM_LOOP_C			: std_logic_vector(23 downto 0);
-- TOP モジュール -------------------------------
	signal MONI_DRP_DEN			: std_logic;
	signal MONI_DRP_DWE			: std_logic;
	signal MONI_DRP_DRDY		: std_logic;
	signal MONI_DRP_EOC			: std_logic;
	signal MONI_DRP_BUSY		: std_logic;
	signal vp_in				: std_logic;
	signal vn_in				: std_logic;
	signal vauxp4				: std_logic;
	signal vauxn4				: std_logic;
	signal vauxp12				: std_logic;
	signal vauxn12				: std_logic;
	-- UART
	signal UART_RX				: std_logic;
	signal UART_TX				: std_logic;
-- UART モジュール(シミュレーション用モデル)
	signal SIM_TX_DATA_IN			: std_logic_vector(7 downto 0);
	signal SIM_TX_DATA_SET			: std_logic;
	signal SIM_TX_BUSY				: std_logic;
	signal SIM_TX_PARITY_ODD_EVEN	: std_logic;
	signal SIM_RX_DATA				: std_logic_vector(7 downto 0);
	signal SIM_RX_RECIEVE_END		: std_logic;
-- 動作確認用LED --------------------------------
	signal LED_ONOFF_OUT			: std_logic;

-- 使用モジュール宣言 -----------------------------------------------------------------------------

-- TOP モジュール -------------------------------
component TOP_FPGA
port (
	-- システム
	nRESET			: in	std_logic;		-- nRESET
	CLK_IN			: in	std_logic;		-- CLOCK 12MHz
	SWITCH_RES_IN	: in	std_logic;		-- RESET用スイッチ(正論理)
	-- DRP信号MONITOR
	MONI_DRP_DEN	: out	std_logic;
	MONI_DRP_DWE	: out	std_logic;
	MONI_DRP_DRDY	: out	std_logic;
	MONI_DRP_EOC	: out	std_logic;
	MONI_DRP_BUSY	: out	std_logic;
	-- XADC アナログ入力信号
	vp_in			: in	std_logic;
	vn_in			: in	std_logic;
	vauxp4			: in	std_logic;
	vauxn4			: in	std_logic;
	vauxp12			: in	std_logic;
	vauxn12			: in	std_logic;
	-- UART
	UART_RX			: in	std_logic;
	UART_TX			: out	std_logic;
	-- LED
	LED_ONOFF_OUT	: out std_logic			-- ロジック動作中LED
);
end component ;

-- UART モジュール(シミュレーション用モデル) ----
component SIM_MODULE_UART_8_bit
port (
	-- システム
	nRESET					: in	std_logic;						-- 外部 RESETIN 入力(負論理)
	CLK_IN					: in	std_logic;						-- クロック	20MHz
	-- 送信
	SIM_TX_DATA_IN			: in	std_logic_vector(7 downto 0);	-- 送信データ
	SIM_TX_DATA_SET			: in	std_logic;						-- 動作開始信号
	SIM_TX_BUSY				: out	std_logic;						-- 送信処理中は '1'、送信終了後 '0'
	SIM_UART_TX				: out	std_logic;
	SIM_TX_PARITY_ODD_EVEN	: in	std_logic;						-- パリティ 0:偶数、1:奇数
	-- 受信
	SIM_UART_RX				: in	std_logic;
	SIM_RX_DATA				: out	std_logic_vector(7 downto 0);	-- 受信データ
	SIM_RX_PARITY_bit		: out	std_logic;						-- 受信したパリティビット
	SIM_RX_PARITY_ODD_EVEN	: out	std_logic;						-- 受信パリティ 0:偶数、1:奇数
	SIM_RX_BUSY				: out	std_logic;						-- 受信処理中は '1'、受信終了後 '0'
	SIM_RX_RECIEVE_END		: out	std_logic						-- 受信終了信号 (1-CLOCK)
);
end component ;

-- プロシージャー（サブ関数）宣言 -----------------------------------------------------------------

begin ---------------------------------------------------------------------------------------------

-- PULL-UP ----------------------------------------------------------------------------------------
--	nRESET	<= 'H';

-- モジュール読み出し -----------------------------------------------------------------------------

-- TOP モジュール -------------------------------
m_TOP_FPGA : TOP_FPGA
port map(
	-- システム
	nRESET			=> nRESET,
	CLK_IN			=> CLK_IN,
	SWITCH_RES_IN	=> SWITCH_RES_IN,
	-- DRP信号MONITOR
	MONI_DRP_DEN	=> MONI_DRP_DEN,
	MONI_DRP_DWE	=> MONI_DRP_DWE,
	MONI_DRP_DRDY	=> MONI_DRP_DRDY,
	MONI_DRP_EOC	=> MONI_DRP_EOC,
	MONI_DRP_BUSY	=> MONI_DRP_BUSY,
	-- XADC アナログ入力信号
	vp_in			=> vp_in,
	vn_in			=> vn_in,
	vauxp4			=> vauxp4,
	vauxn4			=> vauxn4,
	vauxp12			=> vauxp12,
	vauxn12			=> vauxn12,
	-- UART
	UART_RX			=> UART_RX,
	UART_TX			=> UART_TX,
	-- LED
	LED_ONOFF_OUT	=> LED_ONOFF_OUT
);

-- UART モジュール(シミュレーション用モデル) ----
m_SIM_MODULE_UART_8_bit : SIM_MODULE_UART_8_bit
port map(
	-- システム
	nRESET					=> nRESET,
	CLK_IN					=> CLK_IN,
	-- 送信
	SIM_TX_DATA_IN			=> SIM_TX_DATA_IN,
	SIM_TX_DATA_SET			=> SIM_TX_DATA_SET,
	SIM_TX_BUSY				=> SIM_TX_BUSY,
	SIM_UART_TX				=> UART_RX,					-- TX
	SIM_TX_PARITY_ODD_EVEN	=> SIM_TX_PARITY_ODD_EVEN,
	-- 受信
	SIM_UART_RX				=> UART_TX,					-- RX
	SIM_RX_DATA				=> SIM_RX_DATA,
	SIM_RX_PARITY_bit		=> open,
	SIM_RX_PARITY_ODD_EVEN	=> open,
	SIM_RX_BUSY				=> open,
	SIM_RX_RECIEVE_END		=> SIM_RX_RECIEVE_END
);

-- クロック生成プロセス ---------------------------------------------------------------------------
-- 12MHz(83.3nsec)
process begin
	CLK_IN	<= '1';
	wait for CYCLE12/2;
	CLK_IN	<= '0';
	wait for CYCLE12/2;
end process;

-- メインシミュレーション -------------------------------------------------------------------------
process begin

-- 初期化 ---------------------------------------
	simulation_title1	<= "ARTY-7 XADC TEST    ";
	simulation_title2	<= "INIT                ";

-- シミュレーション用初期化 ---------------------
	SIM_LOOP_C 	<= (others => '0');
	wait until rising_edge(CLK_IN);

-- 入力ピン初期化 -------------------------------
	wait until rising_edge(CLK_IN);
	SWITCH_RES_IN			<= '0';
	nRESET					<= '0';

	SIM_TX_DATA_IN			<= (others => '0');
	SIM_TX_DATA_SET			<= '0';
	SIM_TX_PARITY_ODD_EVEN	<= '0';

	wait until rising_edge(CLK_IN);
	wait until rising_edge(CLK_IN);

-- nRESET 発生 ----------------------------------
	simulation_title2	<= "nRESET              ";
	wait until	rising_edge(CLK_IN);
	nRESET				<= '0';
	wait until	rising_edge(CLK_IN);
	wait until	rising_edge(CLK_IN);
	wait until	rising_edge(CLK_IN);
	wait until	rising_edge(CLK_IN);
	nRESET				<= '1';
	wait until	rising_edge(CLK_IN);
	wait until	rising_edge(CLK_IN);

-- MMCM(PLL)安定待ち ----------------------------
-- VIVADOのシミュレーションでは、起動に時間が掛かる
	simulation_title2	<= "WAIT MMCM START     ";
	wait until	rising_edge(CLK_IN);
	wait for 50 uS;
	wait until	rising_edge(CLK_IN);

-- UART 受信データ確認 --------------------------

	simulation_title2		<= "WAIT 0Dh            ";
	wait until rising_edge(CLK_IN) ;

	-- SIM側 [0Dh] 受信待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK_IN) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE12 - 1 nS;
		exit when (( SIM_RX_RECIEVE_END = '1' ) and ( SIM_RX_DATA = X"0D" ));
		exit when ( SIM_LOOP_C > X"0F0000" );	-- TIME OUT
	end loop;

	wait until rising_edge(CLK_IN) ;
	wait for CYCLE12 - 1 nS;
	-- CHECK (時間は不問)
	if ( SIM_RX_DATA /= X"0D" ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 様子見
	wait until rising_edge(CLK_IN) ;
	simulation_title2		<= "WAIT AND SEE        ";
	wait until rising_edge(CLK_IN) ;
	wait for 100 uS;
	wait until rising_edge(CLK_IN) ;


-- 終了[完走] -------------------------------------------------------------------------------------
	wait until rising_edge(CLK_IN) ;
	simulation_title1	<= "[ END ]             ";
	simulation_title2	<= "[ END ]             ";
	wait until rising_edge(CLK_IN) ;
--	wait for 1 uS;
	assert (false)	report "    <<<<<<<<<< END : The simulation was successful >>>>>>>>>>" severity failure;
	wait;

end process;


-- END --------------------------------------------------------------------------------------------
-- (C) 2025 JAPAN LOGIC DESIGN 日本ロジック設計
-- No unauthorized reproduction or AI training allowed.
-- Unauthorized reproduction prohibited.
end SIM;

