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// MODULE VLNV: xilinx.com:ip:xadc_wiz:3.3

`timescale 1ps / 1ps

`include "vivado_interfaces.svh"

module xadc_wiz_0_sv (
  (* X_INTERFACE_IGNORE = "true" *)
  input wire [15:0] di_in,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire [6:0] daddr_in,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire den_in,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire dwe_in,
  (* X_INTERFACE_IGNORE = "true" *)
  output wire drdy_out,
  (* X_INTERFACE_IGNORE = "true" *)
  output wire [15:0] do_out,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire dclk_in,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire reset_in,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire vp_in,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire vn_in,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire vauxp4,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire vauxn4,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire vauxp12,
  (* X_INTERFACE_IGNORE = "true" *)
  input wire vauxn12,
  (* X_INTERFACE_IGNORE = "true" *)
  output wire [4:0] channel_out,
  (* X_INTERFACE_IGNORE = "true" *)
  output wire eoc_out,
  (* X_INTERFACE_IGNORE = "true" *)
  output wire alarm_out,
  (* X_INTERFACE_IGNORE = "true" *)
  output wire eos_out,
  (* X_INTERFACE_IGNORE = "true" *)
  output wire busy_out
);

  xadc_wiz_0 inst (
    .di_in(di_in),
    .daddr_in(daddr_in),
    .den_in(den_in),
    .dwe_in(dwe_in),
    .drdy_out(drdy_out),
    .do_out(do_out),
    .dclk_in(dclk_in),
    .reset_in(reset_in),
    .vp_in(vp_in),
    .vn_in(vn_in),
    .vauxp4(vauxp4),
    .vauxn4(vauxn4),
    .vauxp12(vauxp12),
    .vauxn12(vauxn12),
    .channel_out(channel_out),
    .eoc_out(eoc_out),
    .alarm_out(alarm_out),
    .eos_out(eos_out),
    .busy_out(busy_out)
  );

endmodule
