xpm_cdc.sv,systemverilog,xpm,../../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../AMDDesignTools/2025.2/Vivado/data/ip/xpm/xpm_VCOMP.vhd,incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"
xadc_wiz_0.vhd,vhdl,xil_defaultlib,../../../../MAIN_001.gen/sources_1/ip/xadc_wiz_0_1/xadc_wiz_0.vhd,incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"
glbl.v,Verilog,xil_defaultlib,glbl.v
