clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../MAIN_001.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../ipstatic"
clk_wiz_0.v,verilog,xil_defaultlib,../../../../MAIN_001.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="C:/AMDDesignTools/2025.2/Vivado/data/rsb/busdef"incdir="../../../ipstatic"
glbl.v,Verilog,xil_defaultlib,glbl.v
