# 
# Synthesis run script generated by Vivado
# 

set TIME_start [clock seconds] 
namespace eval ::optrace {
  variable script "E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.runs/synth_1/TOP_FPGA.tcl"
  variable category "vivado_synth"
}

# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
  namespace eval ::dispatch {
    variable connected false
    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
      set result "true"
      if {[catch {
        if {[lsearch -exact [package names] DispatchTcl] < 0} {
          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
        }
        if {$result eq "false"} {
          puts "WARNING: Could not load dispatch client library"
        }
        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
        if { $connect_id eq "" } {
          puts "WARNING: Could not initialize dispatch client"
        } else {
          puts "INFO: Dispatch client connection id - $connect_id"
          set connected true
        }
      } catch_res]} {
        puts "WARNING: failed to connect to dispatch server - $catch_res"
      }
    }
  }
}
if {$::dispatch::connected} {
  # Remove the dummy proc if it exists.
  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
    rename ::OPTRACE ""
  }
  proc ::OPTRACE { task action {tags {} } } {
    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
  }
  # dispatch is generic. We specifically want to attach logging.
  ::vitis_log::connect_client
} else {
  # Add dummy proc if it doesn't exist.
  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
        # Do nothing
    }
  }
}

OPTRACE "synth_1" START { ROLLUP_AUTO }
set_param general.usePosixSpawnForFork 1
set_msg_config  -id {Place 30-99}  -string {{ERROR: [Place 30-99] Placer failed with error: 'Unable to place all the instance of site type XADC'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.}}  -suppress 
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7a35tcpg236-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.cache/wt [current_project]
set_property parent.project_path E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.xpr [current_project]
set_property XPM_LIBRARIES XPM_CDC [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_output_repo e:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_vhdl -library xil_defaultlib {
  E:/XILINX_WORK/JapanLogicDesign/A7_XADC/LED_BLINK.vhd
  E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MODULE_UART_8_bit.VHD
  E:/XILINX_WORK/JapanLogicDesign/A7_XADC/array_DEFINITION.VHD
  E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MODULE_XADC_DRP.VHD
  E:/XILINX_WORK/JapanLogicDesign/A7_XADC/NOISE_REDUCTION.VHD
  E:/XILINX_WORK/JapanLogicDesign/A7_XADC/UART_SEND_HEX.vhd
  E:/XILINX_WORK/JapanLogicDesign/A7_XADC/TOP_FPGA.vhd
}
read_ip -quiet E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
set_property used_in_implementation false [get_files -all e:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc]
set_property used_in_implementation false [get_files -all e:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]
set_property used_in_implementation false [get_files -all e:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]

read_ip -quiet E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.srcs/sources_1/ip/xadc_wiz_0_1/xadc_wiz_0.xci
set_property used_in_implementation false [get_files -all e:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.gen/sources_1/ip/xadc_wiz_0_1/xadc_wiz_0_ooc.xdc]
set_property used_in_implementation false [get_files -all e:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.gen/sources_1/ip/xadc_wiz_0_1/xadc_wiz_0.xdc]

OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc E:/XILINX_WORK/JapanLogicDesign/A7_XADC/XDC_FILE.xdc
set_property used_in_implementation false [get_files E:/XILINX_WORK/JapanLogicDesign/A7_XADC/XDC_FILE.xdc]

set_param ips.enableIPCacheLiteLoad 1

read_checkpoint -auto_incremental -incremental E:/XILINX_WORK/JapanLogicDesign/A7_XADC/MAIN_001.srcs/utils_1/imports/synth_1/TOP_A7_UART_TERM.dcp
close [open __synthesis_is_running__ w]

OPTRACE "synth_design" START { }
synth_design -top TOP_FPGA -part xc7a35tcpg236-1
OPTRACE "synth_design" END { }
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
 send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}


OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef TOP_FPGA.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
generate_parallel_reports -reports { "report_utilization -file TOP_FPGA_utilization_synth.rpt -pb TOP_FPGA_utilization_synth.pb"  } 
OPTRACE "synth reports" END { }
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "synth_1" END { }
