---------------------------------------------------------------------------------------------------
-- TEST_BENCH_UART_8_bit.VHD
-- Copyright 2025 日本ロジック設計
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-- <<<<<   No unauthorized reproduction or AI training allowed.   >>>>>

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-- Ver : Date		: Description
-- 0.1 : 2025.05.21	: 1st Version
-- 0.2 : 2025.11.06	: クロック周期測定を追加
-- 0.3 : 2025.11.09	: 通信スタート直後に、送信データ／パリティを変更しても問題ないか確認
---------------------------------------------------------------------------------------------------
-- 解説:
--	[MODULE_UART_8_bit.VHD]用のテストベンチ。
--	1. 通信相手として[SIM_MODULE_UART_8_bit.VHD]を接続し、送受信テストを行う。
--	2. シリアルデータの両端ビット(bit-0, bit-7)を必ず変化させてテストする。
--	3. パリティテストは、偶数／奇数パリティ両方のテストを行う。
--	※ ModelSim, Vivadoシミュレーション で共有できる記述としてある。
---------------------------------------------------------------------------------------------------


-- Use IEEE library -------------------------------------------------------------------------------
library	IEEE;
use		IEEE.STD_LOGIC_1164.ALL;
use		IEEE.STD_LOGIC_ARITH.ALL;
use		IEEE.STD_LOGIC_UNSIGNED.ALL;
use		IEEE.STD_LOGIC_MISC.ALL;

use		IEEE.std_logic_textio.all;
use		std.textio.all;


-- エンティティ宣言 -------------------------------------------------------------------------------
entity TEST_BENCH is
end TEST_BENCH;

architecture SIM of TEST_BENCH is -----------------------------------------------------------------


-- 固定値定義 -------------------------------------------------------------------------------------
	constant	CYCLE20 :	time := 50 ns;	-- クロック 20MHz


-- 信号定義 ---------------------------------------------------------------------------------------

-- タイトル用 -------------------------------
	signal simulation_title1		: string( 1 to 20 );		-- WAVEの上側に表示するタイトル
	signal simulation_title2		: string( 1 to 20 );

	-- システム ---------------------------------
	signal CLK20M					: std_logic;
	signal nRESET					: std_logic;
	signal SIM_LOOP_C				: std_logic_vector(23 downto 0);

	-- UART モジュール(本体)
	signal TX_DATA_IN				: std_logic_vector(7 downto 0);
	signal TX_DATA_SET				: std_logic;
	signal TX_BUSY					: std_logic;
	signal TX_PARITY_ODD_EVEN		: std_logic;
	signal RX_PARITY_ODD_EVEN		: std_logic;
	signal RX_DATA					: std_logic_vector(7 downto 0);
	signal RX_PARITY_bit			: std_logic;
	signal RX_BUSY					: std_logic;
	signal RX_RECIEVE_END			: std_logic;

	-- UART -------------------------------------
	signal UART_TX					: std_logic;
	signal UART_RX					: std_logic;
	-- UART モジュール(シミュレーション用モデル)
	signal SIM_TX_DATA_IN			: std_logic_vector(7 downto 0);
	signal SIM_TX_DATA_SET			: std_logic;
	signal SIM_TX_BUSY				: std_logic;
	signal SIM_TX_PARITY_ODD_EVEN	: std_logic;
	signal SIM_RX_PARITY_ODD_EVEN	: std_logic;
	signal SIM_RX_DATA				: std_logic_vector(7 downto 0);
	signal SIM_RX_PARITY_bit		: std_logic;
	signal SIM_RX_BUSY				: std_logic;
	signal SIM_RX_RECIEVE_END		: std_logic;


-- 使用モジュール宣言 -----------------------------------------------------------------------------

-- UART モジュール(本体) ------------------------
component MODULE_UART_8_bit
port (
	-- システム
	nRESET				: in	std_logic;						-- 外部 RESETIN 入力(負論理)
	CLK20M				: in	std_logic;						-- クロック	20MHz
	-- 送信
	TX_DATA_IN			: in	std_logic_vector(7 downto 0);	-- 送信データ
	TX_DATA_SET			: in	std_logic;						-- 動作開始信号
	TX_BUSY				: out	std_logic;						-- 送信処理中は '1'、送信終了後 '0'
	UART_TX				: out	std_logic;
	TX_PARITY_ODD_EVEN	: in	std_logic;						-- パリティ 0:偶数、1:奇数
	-- 受信
	UART_RX				: in	std_logic;
	RX_DATA				: out	std_logic_vector(7 downto 0);	-- 受信データ
	RX_PARITY_bit		: out	std_logic;						-- 受信したパリティビット
	RX_PARITY_ODD_EVEN	: out	std_logic;						-- 受信パリティ 0:偶数、1:奇数
	RX_BUSY				: out	std_logic;						-- 受信処理中は '1'、受信終了後 '0'
	RX_RECIEVE_END		: out	std_logic						-- 受信終了信号 (1-CLOCK)
);
end component ;

-- UART モジュール(シミュレーション用モデル) ----
component SIM_MODULE_UART_8_bit
port (
	-- システム
	nRESET					: in	std_logic;						-- 外部 RESETIN 入力(負論理)
	CLK20M					: in	std_logic;						-- クロック	20MHz
	-- 送信
	SIM_TX_DATA_IN			: in	std_logic_vector(7 downto 0);	-- 送信データ
	SIM_TX_DATA_SET			: in	std_logic;						-- 動作開始信号
	SIM_TX_BUSY				: out	std_logic;						-- 送信処理中は '1'、送信終了後 '0'
	SIM_UART_TX				: out	std_logic;
	SIM_TX_PARITY_ODD_EVEN	: in	std_logic;						-- パリティ 0:偶数、1:奇数
	-- 受信
	SIM_UART_RX				: in	std_logic;
	SIM_RX_DATA				: out	std_logic_vector(7 downto 0);	-- 受信データ
	SIM_RX_PARITY_bit		: out	std_logic;						-- 受信したパリティビット
	SIM_RX_PARITY_ODD_EVEN	: out	std_logic;						-- 受信パリティ 0:偶数、1:奇数
	SIM_RX_BUSY				: out	std_logic;						-- 受信処理中は '1'、受信終了後 '0'
	SIM_RX_RECIEVE_END		: out	std_logic						-- 受信終了信号 (1-CLOCK)
);
end component ;

-- プロシージャー（サブ関数）宣言 -----------------------------------------------------------------


begin ---------------------------------------------------------------------------------------------


-- モジュール読み出し -----------------------------------------------------------------------------

-- UART モジュール(本体) ------------------------
m_MODULE_UART_8_bit : MODULE_UART_8_bit
port map(
	-- システム
	nRESET				=> nRESET,
	CLK20M				=> CLK20M,
	-- 送信
	TX_DATA_IN			=> TX_DATA_IN,
	TX_DATA_SET			=> TX_DATA_SET,
	TX_BUSY				=> TX_BUSY,
	UART_TX				=> UART_TX,					-- TX
	TX_PARITY_ODD_EVEN	=> TX_PARITY_ODD_EVEN,
	-- 受信
	UART_RX				=> UART_RX,					-- RX
	RX_DATA				=> RX_DATA,
	RX_PARITY_bit		=> RX_PARITY_bit,
	RX_PARITY_ODD_EVEN	=> RX_PARITY_ODD_EVEN,
	RX_BUSY				=> RX_BUSY,
	RX_RECIEVE_END		=> RX_RECIEVE_END
);

-- UART モジュール(シミュレーション用モデル) ----
m_SIM_MODULE_UART_8_bit : SIM_MODULE_UART_8_bit
port map(
	-- システム
	nRESET					=> nRESET,
	CLK20M					=> CLK20M,
	-- 送信
	SIM_TX_DATA_IN			=> SIM_TX_DATA_IN,
	SIM_TX_DATA_SET			=> SIM_TX_DATA_SET,
	SIM_TX_BUSY				=> SIM_TX_BUSY,
	SIM_UART_TX				=> UART_RX,					-- TX
	SIM_TX_PARITY_ODD_EVEN	=> SIM_TX_PARITY_ODD_EVEN,
	-- 受信
	SIM_UART_RX				=> UART_TX,					-- RX
	SIM_RX_DATA				=> SIM_RX_DATA,
	SIM_RX_PARITY_bit		=> SIM_RX_PARITY_bit,
	SIM_RX_PARITY_ODD_EVEN	=> SIM_RX_PARITY_ODD_EVEN,
	SIM_RX_BUSY				=> SIM_RX_BUSY,
	SIM_RX_RECIEVE_END		=> SIM_RX_RECIEVE_END
);

-- クロック生成プロセス ---------------------------------------------------------------------------
-- 20MHz(50nsec)
process begin
	CLK20M	<= '1';
	wait for CYCLE20/2;
	CLK20M	<= '0';
	wait for CYCLE20/2;
end process;


-- メインシミュレーション -------------------------------------------------------------------------
process begin

-- 初期化 ---------------------------------------
	simulation_title1	<= "INIT                ";
	simulation_title2	<= "INIT                ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

-- 入力ピン初期化 -------------------------------
	nRESET	 				<= '1';			-- '1'
	TX_DATA_IN				<= (others => '0');
	TX_DATA_SET				<= '0';
	TX_PARITY_ODD_EVEN		<= '0';			-- パリティ 0:偶数
	SIM_TX_DATA_IN			<= (others => '0');
	SIM_TX_DATA_SET			<= '0';
	SIM_TX_PARITY_ODD_EVEN	<= '0';			-- パリティ 0:偶数

-- シミュレーション用初期化 ---------------------
	SIM_LOOP_C		 		<= (others => '0');
	wait until rising_edge(CLK20M) ;

-- RESET 発生 -----------------------------------
	simulation_title2		<= "RESET               ";
	wait until	rising_edge(CLK20M);
	wait for 1 nS;
	nRESET					<= '0' after 10 nS ;	-- '0' 非同期入力 RESET
	wait until	rising_edge(CLK20M);
	wait until	rising_edge(CLK20M);
	wait for 1 nS;
	nRESET					<= '1' after 10 nS ;	-- '1' 非同期入力 RESET
	wait until	rising_edge(CLK20M);
	wait until	rising_edge(CLK20M);

-- 送信テスト:パリティ[偶数] ----------------------------------------------------------------------

	-- パリティ[偶数] ---------------------------
	simulation_title1		<= "UART TEST[EVEN]     ";
	wait until	rising_edge(CLK20M);
	wait for 1 nS;

	-- 送信 MAIN->SIM:81h -----------------------
	simulation_title2		<= "MAIN->SIM:81h       ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信BUSY 解除待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( TX_BUSY = '0' );			-- BUSY解除待ち
		exit when ( SIM_LOOP_C > X"001000" );	-- TIME OUT
	end loop;
	-- CHECK (時間は不問)
	if ( TX_BUSY /= '0' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信(MAIN)
	TX_DATA_IN				<= X"81";
	TX_PARITY_ODD_EVEN		<= '0';

	TX_DATA_SET				<= '1';
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	TX_DATA_SET				<= '0';

	-- 通信スタート直後に、送信データ／パリティを変更しても問題ないか確認
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	TX_DATA_IN				<= X"55";
	TX_PARITY_ODD_EVEN		<= '1';

	-- 受信待ち(SIM)
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( SIM_RX_RECIEVE_END = '1' );	-- 受信終了信号待ち(1-CLOCK)
		exit when ( SIM_LOOP_C > X"001000" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( SIM_RX_RECIEVE_END /= '1' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;
	if ( SIM_LOOP_C /= X"00089B" ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 受信データ確認
	if ( SIM_RX_DATA /= X"81" ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 受信パリティ:[偶数]確認
	if ( SIM_RX_PARITY_ODD_EVEN /= '0' ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;


	-- 送信 MAIN->SIM:7Eh -----------------------
	simulation_title2		<= "MAIN->SIM:7Eh       ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信BUSY 解除待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( TX_BUSY = '0' );			-- BUSY解除待ち
		exit when ( SIM_LOOP_C > X"000100" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( TX_BUSY /= '0' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;
	if ( SIM_LOOP_C /= X"0000C4" ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信(MAIN)
	TX_DATA_IN				<= X"7E";
	TX_PARITY_ODD_EVEN		<= '0';

	TX_DATA_SET				<= '1';
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	TX_DATA_SET				<= '0';

	-- 受信待ち(SIM)
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( SIM_RX_RECIEVE_END = '1' );	-- 受信終了信号待ち(1-CLOCK)
		exit when ( SIM_LOOP_C > X"004000" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( SIM_RX_RECIEVE_END /= '1' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;
	if ( SIM_LOOP_C /= X"00089C" ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 受信データ確認
	if ( SIM_RX_DATA /= X"7E" ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 受信パリティ:[偶数]確認
	if ( SIM_RX_PARITY_ODD_EVEN /= '0' ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;


	-- 送信 MAIN->SIM:02h -----------------------
	simulation_title2		<= "MAIN->SIM:02h       ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信BUSY 解除待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( TX_BUSY = '0' );			-- BUSY解除待ち
		exit when ( SIM_LOOP_C > X"001000" );	-- TIME OUT
	end loop;
	-- CHECK (時間は不問)
	if ( TX_BUSY /= '0' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信(MAIN)
	TX_DATA_IN				<= X"02";
	TX_PARITY_ODD_EVEN		<= '0';

	TX_DATA_SET				<= '1';
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	TX_DATA_SET				<= '0';

	-- 受信待ち(SIM)
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( SIM_RX_RECIEVE_END = '1' );	-- 受信終了信号待ち(1-CLOCK)
		exit when ( SIM_LOOP_C > X"004000" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( SIM_RX_RECIEVE_END /= '1' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 受信データ確認
	if ( SIM_RX_DATA /= X"02" ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 受信パリティ:[偶数]確認
	if ( SIM_RX_PARITY_ODD_EVEN /= '0' ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;


	-- 送信 MAIN->SIM:40h -----------------------
	simulation_title2		<= "MAIN->SIM:40h       ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信BUSY 解除待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( TX_BUSY = '0' );			-- BUSY解除待ち
		exit when ( SIM_LOOP_C > X"001000" );	-- TIME OUT
	end loop;
	-- CHECK (時間は不問)
	if ( TX_BUSY /= '0' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信(MAIN)
	TX_DATA_IN				<= X"40";
	TX_PARITY_ODD_EVEN		<= '0';

	TX_DATA_SET				<= '1';
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	TX_DATA_SET				<= '0';

	-- 受信待ち(SIM)
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( SIM_RX_RECIEVE_END = '1' );	-- 受信終了信号待ち(1-CLOCK)
		exit when ( SIM_LOOP_C > X"004000" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( SIM_RX_RECIEVE_END /= '1' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 受信データ確認
	if ( SIM_RX_DATA /= X"40" ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 受信パリティ:[偶数]確認
	if ( SIM_RX_PARITY_ODD_EVEN /= '0' ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;


	-- 送信 SIM->MAIN:81h -----------------------
	simulation_title2		<= "SIM->MAIN:81h       ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信BUSY 解除待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( SIM_TX_BUSY = '0' );		-- BUSY解除待ち
		exit when ( SIM_LOOP_C > X"001000" );	-- TIME OUT
	end loop;
	-- CHECK (時間は不問)
	if ( SIM_TX_BUSY /= '0' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信(SIM)
	SIM_TX_DATA_IN			<= X"81";
	SIM_TX_PARITY_ODD_EVEN	<= '0';

	SIM_TX_DATA_SET			<= '1';
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	SIM_TX_DATA_SET			<= '0';

	-- 受信待ち(MAIN)
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( RX_RECIEVE_END = '1' );	-- 受信終了信号待ち(1-CLOCK)
		exit when ( SIM_LOOP_C > X"004000" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( RX_RECIEVE_END /= '1' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 受信データ確認
	if ( RX_DATA /= X"81" ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 受信パリティ:[偶数]確認
	if ( RX_PARITY_ODD_EVEN /= '0' ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;


-- 送信テスト:パリティ[奇数] ----------------------------------------------------------------------

	-- パリティ [奇数] --------------------------
	simulation_title1		<= "UART TEST[ODD]      ";
	wait until	rising_edge(CLK20M);
	wait for 1 nS;

	-- 送信 MAIN->SIM:91h -----------------------
	simulation_title2		<= "MAIN->SIM:91h       ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信BUSY 解除待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( TX_BUSY = '0' );			-- BUSY解除待ち
		exit when ( SIM_LOOP_C > X"001000" );	-- TIME OUT
	end loop;
	-- CHECK (時間は不問)
	if ( TX_BUSY /= '0' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信(MAIN)
	TX_DATA_IN				<= X"91";
	TX_PARITY_ODD_EVEN		<= '1';

	TX_DATA_SET				<= '1';
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	TX_DATA_SET				<= '0';

	-- 受信待ち(SIM)
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( SIM_RX_RECIEVE_END = '1' );	-- 受信終了信号待ち(1-CLOCK)
		exit when ( SIM_LOOP_C > X"004000" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( SIM_RX_RECIEVE_END /= '1' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 受信データ確認
	if ( SIM_RX_DATA /= X"91" ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 受信パリティ:[奇数]確認
	if ( SIM_RX_PARITY_ODD_EVEN /= '1' ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 送信 SIM->MAIN:04h -----------------------
	simulation_title2		<= "SIM->MAIN:04h       ";
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信BUSY 解除待ち
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( SIM_TX_BUSY = '0' );		-- BUSY解除待ち
		exit when ( SIM_LOOP_C > X"001000" );	-- TIME OUT
	end loop;
	-- CHECK (時間は不問)
	if ( SIM_TX_BUSY /= '0' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	wait until rising_edge(CLK20M) ;
	wait for 1 nS;

	-- 送信(SIM)
	SIM_TX_DATA_IN			<= X"04";
	SIM_TX_PARITY_ODD_EVEN	<= '1';

	SIM_TX_DATA_SET			<= '1';
	wait until rising_edge(CLK20M) ;
	wait for 1 nS;
	SIM_TX_DATA_SET			<= '0';

	-- 受信待ち(MAIN)
	SIM_LOOP_C				<= (others => '0');
	while ( true )  loop
		wait until rising_edge(CLK20M) ;
		wait for 1 nS;
		SIM_LOOP_C		<= SIM_LOOP_C + '1';
		wait for CYCLE20 - 3 nS;
		exit when ( RX_RECIEVE_END = '1' );	-- 受信終了信号待ち(1-CLOCK)
		exit when ( SIM_LOOP_C > X"004000" );	-- TIME OUT
	end loop;
	-- CHECK
	if ( RX_RECIEVE_END /= '1' ) then	report "<<<<<<< TIME-OUT >>>>>>>" severity failure;
	end if;

	-- 受信データ確認
	if ( RX_DATA /= X"04" ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- 受信パリティ:[奇数]確認
	if ( RX_PARITY_ODD_EVEN /= '1' ) then	report "<<<<<<<  ERROR >>>>>>>" severity failure;
	end if;

	-- STOP -------------------------------------
	simulation_title2	<= "[STOP]              ";
	wait until rising_edge(CLK20M) ;
	wait for 30 uS;
	wait until rising_edge(CLK20M) ;


-- 終了[完走] -------------------------------------------------------------------------------------
	wait until rising_edge(CLK20M) ;
	simulation_title1	<= "[ END ]             ";
	simulation_title2	<= "[ END ]             ";
	wait until rising_edge(CLK20M) ;
	assert (false)	report "    <<<<<<<<<< END : The simulation was successful >>>>>>>>>>" severity failure;
	wait;

end process;


-- END --------------------------------------------------------------------------------------------
-- Copyright 2025 JAPAN LOGIC DESIGN 日本ロジック設計
end SIM;


