// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (win64) Build 6299465 Fri Nov 14 19:35:11 GMT 2025
// Date        : Wed Dec 17 05:49:00 2025
// Host        : intel_14700k running 64-bit major release  (build 9200)
// Command     : write_verilog -mode timesim -nolib -sdf_anno true -force -file
//               E:/XILINX_WORK/JapanLogicDesign/UART_8_bit/MAIN_001.sim/sim_1/impl/timing/xsim/TEST_BENCH_time_impl.v
// Design      : MODULE_UART_8_bit
// Purpose     : This verilog netlist is a timing simulation representation of the design and should not be modified or
//               synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device      : xc7s50csga324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING

(* CLOCK_DIV_VALUE = "99" *) (* ECO_CHECKSUM = "44791ed5" *) 
(* NotValidForBitStream *)
(* \DesignAttr:ENABLE_NOC_NETLIST_VIEW  *) 
(* \DesignAttr:ENABLE_AIE_NETLIST_VIEW  *) 
module MODULE_UART_8_bit
   (nRESET,
    CLK20M,
    TX_DATA_IN,
    TX_DATA_SET,
    TX_BUSY,
    UART_TX,
    TX_PARITY_ODD_EVEN,
    UART_RX,
    RX_DATA,
    RX_PARITY_bit,
    RX_PARITY_ODD_EVEN,
    RX_BUSY,
    RX_RECIEVE_END);
  input nRESET;
  input CLK20M;
  input [7:0]TX_DATA_IN;
  input TX_DATA_SET;
  output TX_BUSY;
  output UART_TX;
  input TX_PARITY_ODD_EVEN;
  input UART_RX;
  output [7:0]RX_DATA;
  output RX_PARITY_bit;
  output RX_PARITY_ODD_EVEN;
  output RX_BUSY;
  output RX_RECIEVE_END;

  wire CLK20M;
  wire CLK20M_IBUF;
  (* CLOCK_BUFFER_TYPE = "BUFG" *) wire CLK20M_IBUF_bufg;
  wire RX_ACTION_F_i_1_n_0;
  wire RX_ACTION_STOP;
  wire \RX_BIT_COUNTER[6]_i_2_n_0 ;
  wire \RX_BIT_COUNTER[7]_i_1_n_0 ;
  wire \RX_BIT_COUNTER[7]_i_4_n_0 ;
  wire [7:0]RX_BIT_COUNTER_reg;
  wire RX_BUSY;
  wire RX_BUSY_OBUF;
  wire \RX_CLK_DIV_C[6]_i_2_n_0 ;
  wire \RX_CLK_DIV_C[7]_i_1_n_0 ;
  wire \RX_CLK_DIV_C[7]_i_3_n_0 ;
  wire [7:0]RX_CLK_DIV_C_reg;
  wire [7:0]RX_DATA;
  wire RX_DATA_LATCH;
  wire [7:0]RX_DATA_OBUF;
  wire [0:0]RX_DATA_SHIFT_f;
  wire \RX_DATA_SHIFT_f[7]_i_2_n_0 ;
  wire \RX_DATA_SHIFT_f[7]_i_3_n_0 ;
  wire \RX_DATA_SHIFT_f[7]_i_4_n_0 ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[0] ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[1] ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[2] ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[3] ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[4] ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[5] ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[6] ;
  wire \RX_DATA_SHIFT_f_reg_n_0_[7] ;
  wire [7:0]RX_DATA_f;
  wire \RX_DATA_f[7]_i_2_n_0 ;
  wire RX_PARITY_CALC;
  wire RX_PARITY_CALC_i_1_n_0;
  wire RX_PARITY_CALC_i_2_n_0;
  wire RX_PARITY_ODD_EVEN;
  wire RX_PARITY_ODD_EVEN_OBUF;
  wire RX_PARITY_bit;
  wire RX_PARITY_bit_OBUF;
  wire RX_PARITY_bit_f;
  wire RX_PARITY_bit_f_i_1_n_0;
  wire RX_PARITY_bit_f_i_2_n_0;
  wire RX_RECIEVE_END;
  wire RX_RECIEVE_END_OBUF;
  wire RX_RECIEVE_END_i_1_n_0;
  wire TX_ACTION_F_i_1_n_0;
  wire TX_ACTION_F_i_2_n_0;
  wire TX_ACTION_F_i_3_n_0;
  wire \TX_BIT_COUNTER[6]_i_2_n_0 ;
  wire \TX_BIT_COUNTER[7]_i_1_n_0 ;
  wire \TX_BIT_COUNTER[7]_i_4_n_0 ;
  wire [7:0]TX_BIT_COUNTER_reg;
  wire TX_BUSY;
  wire TX_BUSY_OBUF;
  wire \TX_CLK_DIV_C[6]_i_2_n_0 ;
  wire \TX_CLK_DIV_C[7]_i_1_n_0 ;
  wire \TX_CLK_DIV_C[7]_i_3_n_0 ;
  wire [7:0]TX_CLK_DIV_C_reg;
  wire [7:0]TX_DATA_IN;
  wire [7:0]TX_DATA_IN_IBUF;
  wire TX_DATA_SET;
  wire TX_DATA_SET_IBUF;
  wire TX_DATA_SET_d;
  wire TX_DATA_SET_d_i_1_n_0;
  wire \TX_DATA_SHIFT[7]_i_1_n_0 ;
  wire \TX_DATA_SHIFT[7]_i_4_n_0 ;
  wire \TX_DATA_SHIFT[7]_i_5_n_0 ;
  wire \TX_DATA_SHIFT_reg_n_0_[0] ;
  wire \TX_DATA_SHIFT_reg_n_0_[1] ;
  wire \TX_DATA_SHIFT_reg_n_0_[2] ;
  wire \TX_DATA_SHIFT_reg_n_0_[3] ;
  wire \TX_DATA_SHIFT_reg_n_0_[4] ;
  wire \TX_DATA_SHIFT_reg_n_0_[5] ;
  wire \TX_DATA_SHIFT_reg_n_0_[6] ;
  wire \TX_DATA_SHIFT_reg_n_0_[7] ;
  wire TX_PARITY_ODD_EVEN;
  wire TX_PARITY_ODD_EVEN_IBUF;
  wire TX_PARITY_ODD_EVEN_d;
  wire TX_PARITY_bit;
  wire TX_PARITY_bit9_out;
  wire TX_PARITY_bit_i_1_n_0;
  wire TX_PARITY_bit_i_3_n_0;
  wire TX_PARITY_bit_i_4_n_0;
  wire TX_TIMING_SHIFT;
  wire UART_RX;
  wire UART_RX_IBUF;
  wire UART_RX_d1;
  wire UART_RX_d2;
  wire UART_RX_d3;
  wire UART_TX;
  wire UART_TX_OBUF;
  wire UART_TX_f6_out;
  wire UART_TX_f_i_3_n_0;
  wire UART_TX_f_i_4_n_0;
  wire UART_TX_f_i_5_n_0;
  wire eqOp13_in;
  wire eqOp19_in;
  wire nRESET;
  wire nRESET_IBUF;
  wire p_15_in;
  wire [7:0]p_2_in;
  wire [7:0]plusOp;
  wire [7:0]plusOp__0;
  wire [7:0]plusOp__1;
  wire [7:0]plusOp__2;

initial begin
 $sdf_annotate("TEST_BENCH_time_impl.sdf",,,,"tool_control");
end
  BUFG CLK20M_IBUF_bufg_inst
       (.I(CLK20M_IBUF),
        .O(CLK20M_IBUF_bufg));
  (* clock_buffer_type = "bufg" *) 
  IBUF CLK20M_IBUF_inst
       (.I(CLK20M),
        .O(CLK20M_IBUF));
  LUT6 #(
    .INIT(64'hCCC8CCC8FFFBCCC8)) 
    RX_ACTION_F_i_1
       (.I0(RX_BIT_COUNTER_reg[0]),
        .I1(RX_BUSY_OBUF),
        .I2(RX_BIT_COUNTER_reg[1]),
        .I3(\RX_DATA_SHIFT_f[7]_i_2_n_0 ),
        .I4(UART_RX_d3),
        .I5(UART_RX_d2),
        .O(RX_ACTION_F_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    RX_ACTION_F_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(RX_ACTION_F_i_1_n_0),
        .Q(RX_BUSY_OBUF),
        .R(TX_DATA_SET_d_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \RX_BIT_COUNTER[0]_i_1 
       (.I0(RX_BIT_COUNTER_reg[0]),
        .O(plusOp__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \RX_BIT_COUNTER[1]_i_1 
       (.I0(RX_BIT_COUNTER_reg[0]),
        .I1(RX_BIT_COUNTER_reg[1]),
        .O(plusOp__2[1]));
  LUT3 #(
    .INIT(8'h78)) 
    \RX_BIT_COUNTER[2]_i_1 
       (.I0(RX_BIT_COUNTER_reg[1]),
        .I1(RX_BIT_COUNTER_reg[0]),
        .I2(RX_BIT_COUNTER_reg[2]),
        .O(plusOp__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \RX_BIT_COUNTER[3]_i_1 
       (.I0(RX_BIT_COUNTER_reg[2]),
        .I1(RX_BIT_COUNTER_reg[0]),
        .I2(RX_BIT_COUNTER_reg[1]),
        .I3(RX_BIT_COUNTER_reg[3]),
        .O(plusOp__2[3]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \RX_BIT_COUNTER[4]_i_1 
       (.I0(RX_BIT_COUNTER_reg[2]),
        .I1(RX_BIT_COUNTER_reg[1]),
        .I2(RX_BIT_COUNTER_reg[0]),
        .I3(RX_BIT_COUNTER_reg[3]),
        .I4(RX_BIT_COUNTER_reg[4]),
        .O(plusOp__2[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \RX_BIT_COUNTER[5]_i_1 
       (.I0(RX_BIT_COUNTER_reg[2]),
        .I1(RX_BIT_COUNTER_reg[4]),
        .I2(RX_BIT_COUNTER_reg[1]),
        .I3(RX_BIT_COUNTER_reg[0]),
        .I4(RX_BIT_COUNTER_reg[3]),
        .I5(RX_BIT_COUNTER_reg[5]),
        .O(plusOp__2[5]));
  LUT6 #(
    .INIT(64'hF7FFFFFF08000000)) 
    \RX_BIT_COUNTER[6]_i_1 
       (.I0(RX_BIT_COUNTER_reg[5]),
        .I1(RX_BIT_COUNTER_reg[3]),
        .I2(\RX_BIT_COUNTER[6]_i_2_n_0 ),
        .I3(RX_BIT_COUNTER_reg[4]),
        .I4(RX_BIT_COUNTER_reg[2]),
        .I5(RX_BIT_COUNTER_reg[6]),
        .O(plusOp__2[6]));
  LUT2 #(
    .INIT(4'h7)) 
    \RX_BIT_COUNTER[6]_i_2 
       (.I0(RX_BIT_COUNTER_reg[0]),
        .I1(RX_BIT_COUNTER_reg[1]),
        .O(\RX_BIT_COUNTER[6]_i_2_n_0 ));
  (* \PinAttr:I1:HOLD_DETOUR  = "1359" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \RX_BIT_COUNTER[7]_i_1 
       (.I0(RX_BUSY_OBUF),
        .I1(nRESET_IBUF),
        .O(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hD2)) 
    \RX_BIT_COUNTER[7]_i_3 
       (.I0(RX_BIT_COUNTER_reg[6]),
        .I1(\RX_BIT_COUNTER[7]_i_4_n_0 ),
        .I2(RX_BIT_COUNTER_reg[7]),
        .O(plusOp__2[7]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \RX_BIT_COUNTER[7]_i_4 
       (.I0(RX_BIT_COUNTER_reg[2]),
        .I1(RX_BIT_COUNTER_reg[4]),
        .I2(RX_BIT_COUNTER_reg[1]),
        .I3(RX_BIT_COUNTER_reg[0]),
        .I4(RX_BIT_COUNTER_reg[3]),
        .I5(RX_BIT_COUNTER_reg[5]),
        .O(\RX_BIT_COUNTER[7]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[0]),
        .Q(RX_BIT_COUNTER_reg[0]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[1]),
        .Q(RX_BIT_COUNTER_reg[1]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[2]),
        .Q(RX_BIT_COUNTER_reg[2]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[3]),
        .Q(RX_BIT_COUNTER_reg[3]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[4]),
        .Q(RX_BIT_COUNTER_reg[4]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[5]),
        .Q(RX_BIT_COUNTER_reg[5]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[6]),
        .Q(RX_BIT_COUNTER_reg[6]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_BIT_COUNTER_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp19_in),
        .D(plusOp__2[7]),
        .Q(RX_BIT_COUNTER_reg[7]),
        .R(\RX_BIT_COUNTER[7]_i_1_n_0 ));
  OBUF RX_BUSY_OBUF_inst
       (.I(RX_BUSY_OBUF),
        .O(RX_BUSY));
  (* \PinAttr:I0:HOLD_DETOUR  = "193" *) 
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \RX_CLK_DIV_C[0]_i_1 
       (.I0(RX_CLK_DIV_C_reg[0]),
        .O(plusOp__1[0]));
  (* \PinAttr:I0:HOLD_DETOUR  = "193" *) 
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \RX_CLK_DIV_C[1]_i_1 
       (.I0(RX_CLK_DIV_C_reg[0]),
        .I1(RX_CLK_DIV_C_reg[1]),
        .O(plusOp__1[1]));
  LUT3 #(
    .INIT(8'h78)) 
    \RX_CLK_DIV_C[2]_i_1 
       (.I0(RX_CLK_DIV_C_reg[1]),
        .I1(RX_CLK_DIV_C_reg[0]),
        .I2(RX_CLK_DIV_C_reg[2]),
        .O(plusOp__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \RX_CLK_DIV_C[3]_i_1 
       (.I0(RX_CLK_DIV_C_reg[2]),
        .I1(RX_CLK_DIV_C_reg[0]),
        .I2(RX_CLK_DIV_C_reg[1]),
        .I3(RX_CLK_DIV_C_reg[3]),
        .O(plusOp__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \RX_CLK_DIV_C[4]_i_1 
       (.I0(RX_CLK_DIV_C_reg[0]),
        .I1(RX_CLK_DIV_C_reg[1]),
        .I2(RX_CLK_DIV_C_reg[2]),
        .I3(RX_CLK_DIV_C_reg[3]),
        .I4(RX_CLK_DIV_C_reg[4]),
        .O(plusOp__1[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \RX_CLK_DIV_C[5]_i_1 
       (.I0(RX_CLK_DIV_C_reg[0]),
        .I1(RX_CLK_DIV_C_reg[1]),
        .I2(RX_CLK_DIV_C_reg[3]),
        .I3(RX_CLK_DIV_C_reg[2]),
        .I4(RX_CLK_DIV_C_reg[4]),
        .I5(RX_CLK_DIV_C_reg[5]),
        .O(plusOp__1[5]));
  LUT6 #(
    .INIT(64'hBFFFFFFF40000000)) 
    \RX_CLK_DIV_C[6]_i_1 
       (.I0(\RX_CLK_DIV_C[6]_i_2_n_0 ),
        .I1(RX_CLK_DIV_C_reg[5]),
        .I2(RX_CLK_DIV_C_reg[3]),
        .I3(RX_CLK_DIV_C_reg[2]),
        .I4(RX_CLK_DIV_C_reg[4]),
        .I5(RX_CLK_DIV_C_reg[6]),
        .O(plusOp__1[6]));
  LUT2 #(
    .INIT(4'h7)) 
    \RX_CLK_DIV_C[6]_i_2 
       (.I0(RX_CLK_DIV_C_reg[0]),
        .I1(RX_CLK_DIV_C_reg[1]),
        .O(\RX_CLK_DIV_C[6]_i_2_n_0 ));
  (* OPT_MODIFIED = "RETARGET" *) 
  (* \PinAttr:I0:HOLD_DETOUR  = "1359" *) 
  LUT3 #(
    .INIT(8'hF7)) 
    \RX_CLK_DIV_C[7]_i_1 
       (.I0(nRESET_IBUF),
        .I1(RX_BUSY_OBUF),
        .I2(eqOp19_in),
        .O(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF00007FFF8000)) 
    \RX_CLK_DIV_C[7]_i_2 
       (.I0(RX_CLK_DIV_C_reg[5]),
        .I1(RX_CLK_DIV_C_reg[0]),
        .I2(RX_CLK_DIV_C_reg[1]),
        .I3(RX_CLK_DIV_C_reg[6]),
        .I4(RX_CLK_DIV_C_reg[7]),
        .I5(\RX_CLK_DIV_C[7]_i_3_n_0 ),
        .O(plusOp__1[7]));
  LUT3 #(
    .INIT(8'h7F)) 
    \RX_CLK_DIV_C[7]_i_3 
       (.I0(RX_CLK_DIV_C_reg[3]),
        .I1(RX_CLK_DIV_C_reg[2]),
        .I2(RX_CLK_DIV_C_reg[4]),
        .O(\RX_CLK_DIV_C[7]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[0]),
        .Q(RX_CLK_DIV_C_reg[0]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[1]),
        .Q(RX_CLK_DIV_C_reg[1]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[2]),
        .Q(RX_CLK_DIV_C_reg[2]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[3]),
        .Q(RX_CLK_DIV_C_reg[3]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[4]),
        .Q(RX_CLK_DIV_C_reg[4]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[5]),
        .Q(RX_CLK_DIV_C_reg[5]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[6]),
        .Q(RX_CLK_DIV_C_reg[6]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_CLK_DIV_C_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp__1[7]),
        .Q(RX_CLK_DIV_C_reg[7]),
        .R(\RX_CLK_DIV_C[7]_i_1_n_0 ));
  OBUF \RX_DATA_OBUF[0]_inst 
       (.I(RX_DATA_OBUF[0]),
        .O(RX_DATA[0]));
  OBUF \RX_DATA_OBUF[1]_inst 
       (.I(RX_DATA_OBUF[1]),
        .O(RX_DATA[1]));
  OBUF \RX_DATA_OBUF[2]_inst 
       (.I(RX_DATA_OBUF[2]),
        .O(RX_DATA[2]));
  OBUF \RX_DATA_OBUF[3]_inst 
       (.I(RX_DATA_OBUF[3]),
        .O(RX_DATA[3]));
  OBUF \RX_DATA_OBUF[4]_inst 
       (.I(RX_DATA_OBUF[4]),
        .O(RX_DATA[4]));
  OBUF \RX_DATA_OBUF[5]_inst 
       (.I(RX_DATA_OBUF[5]),
        .O(RX_DATA[5]));
  OBUF \RX_DATA_OBUF[6]_inst 
       (.I(RX_DATA_OBUF[6]),
        .O(RX_DATA[6]));
  OBUF \RX_DATA_OBUF[7]_inst 
       (.I(RX_DATA_OBUF[7]),
        .O(RX_DATA[7]));
  LUT3 #(
    .INIT(8'h0E)) 
    \RX_DATA_SHIFT_f[7]_i_1 
       (.I0(RX_BIT_COUNTER_reg[1]),
        .I1(\RX_DATA_SHIFT_f[7]_i_2_n_0 ),
        .I2(\RX_DATA_SHIFT_f[7]_i_3_n_0 ),
        .O(RX_DATA_SHIFT_f));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \RX_DATA_SHIFT_f[7]_i_2 
       (.I0(RX_BIT_COUNTER_reg[6]),
        .I1(RX_BIT_COUNTER_reg[7]),
        .I2(RX_BIT_COUNTER_reg[3]),
        .I3(RX_BIT_COUNTER_reg[5]),
        .I4(RX_BIT_COUNTER_reg[4]),
        .I5(RX_BIT_COUNTER_reg[2]),
        .O(\RX_DATA_SHIFT_f[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \RX_DATA_SHIFT_f[7]_i_3 
       (.I0(\RX_DATA_SHIFT_f[7]_i_4_n_0 ),
        .I1(RX_CLK_DIV_C_reg[4]),
        .I2(RX_CLK_DIV_C_reg[3]),
        .I3(RX_CLK_DIV_C_reg[2]),
        .I4(RX_BIT_COUNTER_reg[0]),
        .O(\RX_DATA_SHIFT_f[7]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \RX_DATA_SHIFT_f[7]_i_4 
       (.I0(RX_CLK_DIV_C_reg[6]),
        .I1(RX_CLK_DIV_C_reg[1]),
        .I2(RX_CLK_DIV_C_reg[0]),
        .I3(RX_CLK_DIV_C_reg[5]),
        .I4(RX_CLK_DIV_C_reg[7]),
        .O(\RX_DATA_SHIFT_f[7]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[1] ),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[0] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[2] ),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[1] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[3] ),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[2] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[4] ),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[3] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[5] ),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[4] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[6] ),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[5] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[7] ),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[6] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_SHIFT_f_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_SHIFT_f),
        .D(UART_RX_d3),
        .Q(\RX_DATA_SHIFT_f_reg_n_0_[7] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  LUT4 #(
    .INIT(16'h0004)) 
    \RX_DATA_f2[7]_i_1 
       (.I0(RX_BIT_COUNTER_reg[0]),
        .I1(RX_BUSY_OBUF),
        .I2(RX_BIT_COUNTER_reg[1]),
        .I3(\RX_DATA_SHIFT_f[7]_i_2_n_0 ),
        .O(RX_ACTION_STOP));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[0]),
        .Q(RX_DATA_OBUF[0]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[1]),
        .Q(RX_DATA_OBUF[1]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[2]),
        .Q(RX_DATA_OBUF[2]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[3]),
        .Q(RX_DATA_OBUF[3]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[4]),
        .Q(RX_DATA_OBUF[4]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[5]),
        .Q(RX_DATA_OBUF[5]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[6]),
        .Q(RX_DATA_OBUF[6]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f2_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_DATA_f[7]),
        .Q(RX_DATA_OBUF[7]),
        .R(TX_DATA_SET_d_i_1_n_0));
  (* OPT_MODIFIED = "RETARGET" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \RX_DATA_f[7]_i_1 
       (.I0(\RX_DATA_f[7]_i_2_n_0 ),
        .I1(RX_BIT_COUNTER_reg[0]),
        .I2(RX_BIT_COUNTER_reg[4]),
        .I3(eqOp19_in),
        .O(RX_DATA_LATCH));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \RX_DATA_f[7]_i_2 
       (.I0(RX_BIT_COUNTER_reg[2]),
        .I1(RX_BIT_COUNTER_reg[5]),
        .I2(RX_BIT_COUNTER_reg[3]),
        .I3(RX_BIT_COUNTER_reg[7]),
        .I4(RX_BIT_COUNTER_reg[6]),
        .I5(RX_BIT_COUNTER_reg[1]),
        .O(\RX_DATA_f[7]_i_2_n_0 ));
  (* OPT_MODIFIED = "RETARGET" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \RX_DATA_f[7]_i_3 
       (.I0(RX_CLK_DIV_C_reg[2]),
        .I1(RX_CLK_DIV_C_reg[3]),
        .I2(RX_CLK_DIV_C_reg[4]),
        .I3(\RX_DATA_SHIFT_f[7]_i_4_n_0 ),
        .O(eqOp19_in));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[0] ),
        .Q(RX_DATA_f[0]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[1] ),
        .Q(RX_DATA_f[1]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[2] ),
        .Q(RX_DATA_f[2]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[3] ),
        .Q(RX_DATA_f[3]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[4] ),
        .Q(RX_DATA_f[4]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[5] ),
        .Q(RX_DATA_f[5]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[6] ),
        .Q(RX_DATA_f[6]),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \RX_DATA_f_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_DATA_LATCH),
        .D(\RX_DATA_SHIFT_f_reg_n_0_[7] ),
        .Q(RX_DATA_f[7]),
        .R(TX_DATA_SET_d_i_1_n_0));
  (* \PinAttr:I0:HOLD_DETOUR  = "1830" *) 
  LUT6 #(
    .INIT(64'hAA002A80AA000000)) 
    RX_PARITY_CALC_i_1
       (.I0(nRESET_IBUF),
        .I1(UART_RX_d3),
        .I2(\RX_DATA_SHIFT_f[7]_i_2_n_0 ),
        .I3(RX_PARITY_CALC),
        .I4(\RX_DATA_SHIFT_f[7]_i_3_n_0 ),
        .I5(RX_PARITY_CALC_i_2_n_0),
        .O(RX_PARITY_CALC_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    RX_PARITY_CALC_i_2
       (.I0(\RX_DATA_f[7]_i_2_n_0 ),
        .I1(RX_BIT_COUNTER_reg[4]),
        .O(RX_PARITY_CALC_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    RX_PARITY_CALC_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(RX_PARITY_CALC_i_1_n_0),
        .Q(RX_PARITY_CALC),
        .R(1'b0));
  OBUF RX_PARITY_ODD_EVEN_OBUF_inst
       (.I(RX_PARITY_ODD_EVEN_OBUF),
        .O(RX_PARITY_ODD_EVEN));
  FDRE #(
    .INIT(1'b0)) 
    RX_PARITY_ODD_EVEN_f_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_PARITY_CALC),
        .Q(RX_PARITY_ODD_EVEN_OBUF),
        .R(TX_DATA_SET_d_i_1_n_0));
  OBUF RX_PARITY_bit_OBUF_inst
       (.I(RX_PARITY_bit_OBUF),
        .O(RX_PARITY_bit));
  FDRE #(
    .INIT(1'b0)) 
    RX_PARITY_bit_f2_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(RX_ACTION_STOP),
        .D(RX_PARITY_bit_f),
        .Q(RX_PARITY_bit_OBUF),
        .R(TX_DATA_SET_d_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    RX_PARITY_bit_f_i_1
       (.I0(UART_RX_d3),
        .I1(RX_PARITY_bit_f_i_2_n_0),
        .I2(RX_BIT_COUNTER_reg[1]),
        .I3(RX_BIT_COUNTER_reg[4]),
        .I4(\RX_DATA_SHIFT_f[7]_i_3_n_0 ),
        .I5(RX_PARITY_bit_f),
        .O(RX_PARITY_bit_f_i_1_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    RX_PARITY_bit_f_i_2
       (.I0(RX_BIT_COUNTER_reg[6]),
        .I1(RX_BIT_COUNTER_reg[7]),
        .I2(RX_BIT_COUNTER_reg[3]),
        .I3(RX_BIT_COUNTER_reg[5]),
        .I4(RX_BIT_COUNTER_reg[2]),
        .O(RX_PARITY_bit_f_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    RX_PARITY_bit_f_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(RX_PARITY_bit_f_i_1_n_0),
        .Q(RX_PARITY_bit_f),
        .R(TX_DATA_SET_d_i_1_n_0));
  OBUF RX_RECIEVE_END_OBUF_inst
       (.I(RX_RECIEVE_END_OBUF),
        .O(RX_RECIEVE_END));
  (* \PinAttr:I3:HOLD_DETOUR  = "1303" *) 
  LUT4 #(
    .INIT(16'h04FF)) 
    RX_RECIEVE_END_i_1
       (.I0(UART_RX_d2),
        .I1(UART_RX_d3),
        .I2(RX_BUSY_OBUF),
        .I3(nRESET_IBUF),
        .O(RX_RECIEVE_END_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    RX_RECIEVE_END_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(RX_ACTION_STOP),
        .Q(RX_RECIEVE_END_OBUF),
        .R(RX_RECIEVE_END_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFD0000FFFDFFFF)) 
    TX_ACTION_F_i_1
       (.I0(TX_ACTION_F_i_2_n_0),
        .I1(TX_BIT_COUNTER_reg[5]),
        .I2(TX_BIT_COUNTER_reg[6]),
        .I3(TX_BIT_COUNTER_reg[7]),
        .I4(TX_BUSY_OBUF),
        .I5(TX_ACTION_F_i_3_n_0),
        .O(TX_ACTION_F_i_1_n_0));
  LUT5 #(
    .INIT(32'h01000000)) 
    TX_ACTION_F_i_2
       (.I0(TX_BIT_COUNTER_reg[0]),
        .I1(TX_BIT_COUNTER_reg[1]),
        .I2(TX_BIT_COUNTER_reg[2]),
        .I3(TX_BIT_COUNTER_reg[4]),
        .I4(TX_BIT_COUNTER_reg[3]),
        .O(TX_ACTION_F_i_2_n_0));
  (* \PinAttr:I1:HOLD_DETOUR  = "1275" *) 
  LUT2 #(
    .INIT(4'hB)) 
    TX_ACTION_F_i_3
       (.I0(TX_DATA_SET_d),
        .I1(TX_DATA_SET_IBUF),
        .O(TX_ACTION_F_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    TX_ACTION_F_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(TX_ACTION_F_i_1_n_0),
        .Q(TX_BUSY_OBUF),
        .R(TX_DATA_SET_d_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \TX_BIT_COUNTER[0]_i_1 
       (.I0(TX_BIT_COUNTER_reg[0]),
        .O(plusOp__0[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \TX_BIT_COUNTER[1]_i_1 
       (.I0(TX_BIT_COUNTER_reg[0]),
        .I1(TX_BIT_COUNTER_reg[1]),
        .O(plusOp__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \TX_BIT_COUNTER[2]_i_1 
       (.I0(TX_BIT_COUNTER_reg[1]),
        .I1(TX_BIT_COUNTER_reg[0]),
        .I2(TX_BIT_COUNTER_reg[2]),
        .O(plusOp__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \TX_BIT_COUNTER[3]_i_1 
       (.I0(TX_BIT_COUNTER_reg[2]),
        .I1(TX_BIT_COUNTER_reg[0]),
        .I2(TX_BIT_COUNTER_reg[1]),
        .I3(TX_BIT_COUNTER_reg[3]),
        .O(plusOp__0[3]));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \TX_BIT_COUNTER[4]_i_1 
       (.I0(TX_BIT_COUNTER_reg[3]),
        .I1(TX_BIT_COUNTER_reg[1]),
        .I2(TX_BIT_COUNTER_reg[0]),
        .I3(TX_BIT_COUNTER_reg[2]),
        .I4(TX_BIT_COUNTER_reg[4]),
        .O(plusOp__0[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \TX_BIT_COUNTER[5]_i_1 
       (.I0(TX_BIT_COUNTER_reg[4]),
        .I1(TX_BIT_COUNTER_reg[2]),
        .I2(TX_BIT_COUNTER_reg[0]),
        .I3(TX_BIT_COUNTER_reg[1]),
        .I4(TX_BIT_COUNTER_reg[3]),
        .I5(TX_BIT_COUNTER_reg[5]),
        .O(plusOp__0[5]));
  LUT6 #(
    .INIT(64'hF7FFFFFF08000000)) 
    \TX_BIT_COUNTER[6]_i_1 
       (.I0(TX_BIT_COUNTER_reg[5]),
        .I1(TX_BIT_COUNTER_reg[3]),
        .I2(\TX_BIT_COUNTER[6]_i_2_n_0 ),
        .I3(TX_BIT_COUNTER_reg[2]),
        .I4(TX_BIT_COUNTER_reg[4]),
        .I5(TX_BIT_COUNTER_reg[6]),
        .O(plusOp__0[6]));
  LUT2 #(
    .INIT(4'h7)) 
    \TX_BIT_COUNTER[6]_i_2 
       (.I0(TX_BIT_COUNTER_reg[0]),
        .I1(TX_BIT_COUNTER_reg[1]),
        .O(\TX_BIT_COUNTER[6]_i_2_n_0 ));
  (* \PinAttr:I1:HOLD_DETOUR  = "1303" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \TX_BIT_COUNTER[7]_i_1 
       (.I0(TX_BUSY_OBUF),
        .I1(nRESET_IBUF),
        .O(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hD2)) 
    \TX_BIT_COUNTER[7]_i_3 
       (.I0(TX_BIT_COUNTER_reg[6]),
        .I1(\TX_BIT_COUNTER[7]_i_4_n_0 ),
        .I2(TX_BIT_COUNTER_reg[7]),
        .O(plusOp__0[7]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \TX_BIT_COUNTER[7]_i_4 
       (.I0(TX_BIT_COUNTER_reg[4]),
        .I1(TX_BIT_COUNTER_reg[2]),
        .I2(TX_BIT_COUNTER_reg[0]),
        .I3(TX_BIT_COUNTER_reg[1]),
        .I4(TX_BIT_COUNTER_reg[3]),
        .I5(TX_BIT_COUNTER_reg[5]),
        .O(\TX_BIT_COUNTER[7]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[0]),
        .Q(TX_BIT_COUNTER_reg[0]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[1]),
        .Q(TX_BIT_COUNTER_reg[1]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[2]),
        .Q(TX_BIT_COUNTER_reg[2]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[3]),
        .Q(TX_BIT_COUNTER_reg[3]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[4]),
        .Q(TX_BIT_COUNTER_reg[4]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[5]),
        .Q(TX_BIT_COUNTER_reg[5]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[6]),
        .Q(TX_BIT_COUNTER_reg[6]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_BIT_COUNTER_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(eqOp13_in),
        .D(plusOp__0[7]),
        .Q(TX_BIT_COUNTER_reg[7]),
        .R(\TX_BIT_COUNTER[7]_i_1_n_0 ));
  OBUF TX_BUSY_OBUF_inst
       (.I(TX_BUSY_OBUF),
        .O(TX_BUSY));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \TX_CLK_DIV_C[0]_i_1 
       (.I0(TX_CLK_DIV_C_reg[0]),
        .O(plusOp[0]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \TX_CLK_DIV_C[1]_i_1 
       (.I0(TX_CLK_DIV_C_reg[0]),
        .I1(TX_CLK_DIV_C_reg[1]),
        .O(plusOp[1]));
  LUT3 #(
    .INIT(8'h78)) 
    \TX_CLK_DIV_C[2]_i_1 
       (.I0(TX_CLK_DIV_C_reg[1]),
        .I1(TX_CLK_DIV_C_reg[0]),
        .I2(TX_CLK_DIV_C_reg[2]),
        .O(plusOp[2]));
  (* \PinAttr:I3:HOLD_DETOUR  = "193" *) 
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \TX_CLK_DIV_C[3]_i_1 
       (.I0(TX_CLK_DIV_C_reg[2]),
        .I1(TX_CLK_DIV_C_reg[0]),
        .I2(TX_CLK_DIV_C_reg[1]),
        .I3(TX_CLK_DIV_C_reg[3]),
        .O(plusOp[3]));
  (* \PinAttr:I3:HOLD_DETOUR  = "193" *) 
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \TX_CLK_DIV_C[4]_i_1 
       (.I0(TX_CLK_DIV_C_reg[0]),
        .I1(TX_CLK_DIV_C_reg[1]),
        .I2(TX_CLK_DIV_C_reg[2]),
        .I3(TX_CLK_DIV_C_reg[3]),
        .I4(TX_CLK_DIV_C_reg[4]),
        .O(plusOp[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \TX_CLK_DIV_C[5]_i_1 
       (.I0(TX_CLK_DIV_C_reg[0]),
        .I1(TX_CLK_DIV_C_reg[1]),
        .I2(TX_CLK_DIV_C_reg[3]),
        .I3(TX_CLK_DIV_C_reg[2]),
        .I4(TX_CLK_DIV_C_reg[4]),
        .I5(TX_CLK_DIV_C_reg[5]),
        .O(plusOp[5]));
  LUT6 #(
    .INIT(64'hBFFFFFFF40000000)) 
    \TX_CLK_DIV_C[6]_i_1 
       (.I0(\TX_CLK_DIV_C[6]_i_2_n_0 ),
        .I1(TX_CLK_DIV_C_reg[5]),
        .I2(TX_CLK_DIV_C_reg[3]),
        .I3(TX_CLK_DIV_C_reg[2]),
        .I4(TX_CLK_DIV_C_reg[4]),
        .I5(TX_CLK_DIV_C_reg[6]),
        .O(plusOp[6]));
  LUT2 #(
    .INIT(4'h7)) 
    \TX_CLK_DIV_C[6]_i_2 
       (.I0(TX_CLK_DIV_C_reg[0]),
        .I1(TX_CLK_DIV_C_reg[1]),
        .O(\TX_CLK_DIV_C[6]_i_2_n_0 ));
  (* OPT_MODIFIED = "RETARGET" *) 
  (* \PinAttr:I1:HOLD_DETOUR  = "1371" *) 
  LUT3 #(
    .INIT(8'hF7)) 
    \TX_CLK_DIV_C[7]_i_1 
       (.I0(TX_BUSY_OBUF),
        .I1(nRESET_IBUF),
        .I2(eqOp13_in),
        .O(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF00007FFF8000)) 
    \TX_CLK_DIV_C[7]_i_2 
       (.I0(TX_CLK_DIV_C_reg[5]),
        .I1(TX_CLK_DIV_C_reg[0]),
        .I2(TX_CLK_DIV_C_reg[1]),
        .I3(TX_CLK_DIV_C_reg[6]),
        .I4(TX_CLK_DIV_C_reg[7]),
        .I5(\TX_CLK_DIV_C[7]_i_3_n_0 ),
        .O(plusOp[7]));
  LUT3 #(
    .INIT(8'h7F)) 
    \TX_CLK_DIV_C[7]_i_3 
       (.I0(TX_CLK_DIV_C_reg[3]),
        .I1(TX_CLK_DIV_C_reg[2]),
        .I2(TX_CLK_DIV_C_reg[4]),
        .O(\TX_CLK_DIV_C[7]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[0]),
        .Q(TX_CLK_DIV_C_reg[0]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[1]),
        .Q(TX_CLK_DIV_C_reg[1]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[2]),
        .Q(TX_CLK_DIV_C_reg[2]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[3]),
        .Q(TX_CLK_DIV_C_reg[3]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[4]),
        .Q(TX_CLK_DIV_C_reg[4]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[5]),
        .Q(TX_CLK_DIV_C_reg[5]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[6]),
        .Q(TX_CLK_DIV_C_reg[6]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_CLK_DIV_C_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(plusOp[7]),
        .Q(TX_CLK_DIV_C_reg[7]),
        .R(\TX_CLK_DIV_C[7]_i_1_n_0 ));
  IBUF \TX_DATA_IN_IBUF[0]_inst 
       (.I(TX_DATA_IN[0]),
        .O(TX_DATA_IN_IBUF[0]));
  IBUF \TX_DATA_IN_IBUF[1]_inst 
       (.I(TX_DATA_IN[1]),
        .O(TX_DATA_IN_IBUF[1]));
  IBUF \TX_DATA_IN_IBUF[2]_inst 
       (.I(TX_DATA_IN[2]),
        .O(TX_DATA_IN_IBUF[2]));
  IBUF \TX_DATA_IN_IBUF[3]_inst 
       (.I(TX_DATA_IN[3]),
        .O(TX_DATA_IN_IBUF[3]));
  IBUF \TX_DATA_IN_IBUF[4]_inst 
       (.I(TX_DATA_IN[4]),
        .O(TX_DATA_IN_IBUF[4]));
  IBUF \TX_DATA_IN_IBUF[5]_inst 
       (.I(TX_DATA_IN[5]),
        .O(TX_DATA_IN_IBUF[5]));
  IBUF \TX_DATA_IN_IBUF[6]_inst 
       (.I(TX_DATA_IN[6]),
        .O(TX_DATA_IN_IBUF[6]));
  IBUF \TX_DATA_IN_IBUF[7]_inst 
       (.I(TX_DATA_IN[7]),
        .O(TX_DATA_IN_IBUF[7]));
  IBUF TX_DATA_SET_IBUF_inst
       (.I(TX_DATA_SET),
        .O(TX_DATA_SET_IBUF));
  (* \PinAttr:I0:HOLD_DETOUR  = "1371" *) 
  LUT1 #(
    .INIT(2'h1)) 
    TX_DATA_SET_d_i_1
       (.I0(nRESET_IBUF),
        .O(TX_DATA_SET_d_i_1_n_0));
  (* \PinAttr:D:HOLD_DETOUR  = "1763" *) 
  FDRE #(
    .INIT(1'b0)) 
    TX_DATA_SET_d_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(TX_DATA_SET_IBUF),
        .Q(TX_DATA_SET_d),
        .R(TX_DATA_SET_d_i_1_n_0));
  (* \PinAttr:I2:HOLD_DETOUR  = "1275" *) 
  (* \PinAttr:I3:HOLD_DETOUR  = "1127" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \TX_DATA_SHIFT[0]_i_1 
       (.I0(\TX_DATA_SHIFT_reg_n_0_[1] ),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_SET_IBUF),
        .I3(TX_DATA_IN_IBUF[0]),
        .O(p_2_in[0]));
  (* \PinAttr:I2:HOLD_DETOUR  = "1700" *) 
  (* \PinAttr:I3:HOLD_DETOUR  = "1661" *) 
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \TX_DATA_SHIFT[1]_i_1 
       (.I0(\TX_DATA_SHIFT_reg_n_0_[2] ),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_SET_IBUF),
        .I3(TX_DATA_IN_IBUF[1]),
        .O(p_2_in[1]));
  (* \PinAttr:I2:HOLD_DETOUR  = "1798" *) 
  (* \PinAttr:I3:HOLD_DETOUR  = "1575" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \TX_DATA_SHIFT[2]_i_1 
       (.I0(\TX_DATA_SHIFT_reg_n_0_[3] ),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_SET_IBUF),
        .I3(TX_DATA_IN_IBUF[2]),
        .O(p_2_in[2]));
  (* \PinAttr:I2:HOLD_DETOUR  = "1797" *) 
  (* \PinAttr:I3:HOLD_DETOUR  = "1462" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \TX_DATA_SHIFT[3]_i_1 
       (.I0(\TX_DATA_SHIFT_reg_n_0_[4] ),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_SET_IBUF),
        .I3(TX_DATA_IN_IBUF[3]),
        .O(p_2_in[3]));
  (* \PinAttr:I2:HOLD_DETOUR  = "1613" *) 
  (* \PinAttr:I3:HOLD_DETOUR  = "1496" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \TX_DATA_SHIFT[4]_i_1 
       (.I0(\TX_DATA_SHIFT_reg_n_0_[5] ),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_SET_IBUF),
        .I3(TX_DATA_IN_IBUF[4]),
        .O(p_2_in[4]));
  (* \PinAttr:I2:HOLD_DETOUR  = "1769" *) 
  (* \PinAttr:I3:HOLD_DETOUR  = "1659" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \TX_DATA_SHIFT[5]_i_1 
       (.I0(\TX_DATA_SHIFT_reg_n_0_[6] ),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_SET_IBUF),
        .I3(TX_DATA_IN_IBUF[5]),
        .O(p_2_in[5]));
  (* \PinAttr:I0:HOLD_DETOUR  = "151" *) 
  (* \PinAttr:I2:HOLD_DETOUR  = "1783" *) 
  (* \PinAttr:I3:HOLD_DETOUR  = "1488" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \TX_DATA_SHIFT[6]_i_1 
       (.I0(\TX_DATA_SHIFT_reg_n_0_[7] ),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_SET_IBUF),
        .I3(TX_DATA_IN_IBUF[6]),
        .O(p_2_in[6]));
  (* OPT_MODIFIED = "RETARGET" *) 
  (* \PinAttr:I1:HOLD_DETOUR  = "1311" *) 
  LUT6 #(
    .INIT(64'hFF44F44444444444)) 
    \TX_DATA_SHIFT[7]_i_1 
       (.I0(TX_DATA_SET_d),
        .I1(TX_DATA_SET_IBUF),
        .I2(TX_BIT_COUNTER_reg[1]),
        .I3(eqOp13_in),
        .I4(\TX_DATA_SHIFT[7]_i_4_n_0 ),
        .I5(TX_BIT_COUNTER_reg[0]),
        .O(\TX_DATA_SHIFT[7]_i_1_n_0 ));
  (* \PinAttr:I0:HOLD_DETOUR  = "1700" *) 
  (* \PinAttr:I2:HOLD_DETOUR  = "1688" *) 
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \TX_DATA_SHIFT[7]_i_2 
       (.I0(TX_DATA_SET_IBUF),
        .I1(TX_DATA_SET_d),
        .I2(TX_DATA_IN_IBUF[7]),
        .O(p_2_in[7]));
  (* OPT_MODIFIED = "RETARGET" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \TX_DATA_SHIFT[7]_i_3 
       (.I0(TX_CLK_DIV_C_reg[2]),
        .I1(TX_CLK_DIV_C_reg[3]),
        .I2(TX_CLK_DIV_C_reg[4]),
        .I3(\TX_DATA_SHIFT[7]_i_5_n_0 ),
        .O(eqOp13_in));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \TX_DATA_SHIFT[7]_i_4 
       (.I0(TX_BIT_COUNTER_reg[2]),
        .I1(TX_BIT_COUNTER_reg[5]),
        .I2(TX_BIT_COUNTER_reg[6]),
        .I3(TX_BIT_COUNTER_reg[7]),
        .I4(TX_BIT_COUNTER_reg[3]),
        .I5(TX_BIT_COUNTER_reg[4]),
        .O(\TX_DATA_SHIFT[7]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \TX_DATA_SHIFT[7]_i_5 
       (.I0(TX_CLK_DIV_C_reg[6]),
        .I1(TX_CLK_DIV_C_reg[1]),
        .I2(TX_CLK_DIV_C_reg[0]),
        .I3(TX_CLK_DIV_C_reg[5]),
        .I4(TX_CLK_DIV_C_reg[7]),
        .O(\TX_DATA_SHIFT[7]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[0] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[0]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[0] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[1] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[1]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[1] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[2] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[2]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[2] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[3] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[3]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[3] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[4] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[4]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[4] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[5] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[5]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[5] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[6] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[6]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[6] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \TX_DATA_SHIFT_reg[7] 
       (.C(CLK20M_IBUF_bufg),
        .CE(\TX_DATA_SHIFT[7]_i_1_n_0 ),
        .D(p_2_in[7]),
        .Q(\TX_DATA_SHIFT_reg_n_0_[7] ),
        .R(TX_DATA_SET_d_i_1_n_0));
  IBUF TX_PARITY_ODD_EVEN_IBUF_inst
       (.I(TX_PARITY_ODD_EVEN),
        .O(TX_PARITY_ODD_EVEN_IBUF));
  (* \PinAttr:I0:HOLD_DETOUR  = "1358" *) 
  LUT2 #(
    .INIT(4'h2)) 
    TX_PARITY_ODD_EVEN_d_i_1
       (.I0(TX_DATA_SET_IBUF),
        .I1(TX_DATA_SET_d),
        .O(p_15_in));
  (* \PinAttr:D:HOLD_DETOUR  = "1612" *) 
  FDRE #(
    .INIT(1'b0)) 
    TX_PARITY_ODD_EVEN_d_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(p_15_in),
        .D(TX_PARITY_ODD_EVEN_IBUF),
        .Q(TX_PARITY_ODD_EVEN_d),
        .R(TX_DATA_SET_d_i_1_n_0));
  (* \PinAttr:I0:HOLD_DETOUR  = "1722" *) 
  LUT6 #(
    .INIT(64'h2A802A802A800000)) 
    TX_PARITY_bit_i_1
       (.I0(nRESET_IBUF),
        .I1(\TX_DATA_SHIFT_reg_n_0_[0] ),
        .I2(TX_PARITY_bit9_out),
        .I3(TX_PARITY_bit),
        .I4(\TX_DATA_SHIFT[7]_i_4_n_0 ),
        .I5(TX_PARITY_bit_i_3_n_0),
        .O(TX_PARITY_bit_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000E0000000B)) 
    TX_PARITY_bit_i_2
       (.I0(UART_TX_f_i_5_n_0),
        .I1(TX_BIT_COUNTER_reg[2]),
        .I2(TX_BIT_COUNTER_reg[0]),
        .I3(TX_PARITY_bit_i_4_n_0),
        .I4(\TX_DATA_SHIFT[7]_i_5_n_0 ),
        .I5(TX_BIT_COUNTER_reg[1]),
        .O(TX_PARITY_bit9_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    TX_PARITY_bit_i_3
       (.I0(TX_BIT_COUNTER_reg[0]),
        .I1(TX_CLK_DIV_C_reg[2]),
        .I2(TX_CLK_DIV_C_reg[3]),
        .I3(TX_CLK_DIV_C_reg[4]),
        .I4(\TX_DATA_SHIFT[7]_i_5_n_0 ),
        .I5(TX_BIT_COUNTER_reg[1]),
        .O(TX_PARITY_bit_i_3_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    TX_PARITY_bit_i_4
       (.I0(TX_CLK_DIV_C_reg[4]),
        .I1(TX_CLK_DIV_C_reg[3]),
        .I2(TX_CLK_DIV_C_reg[2]),
        .O(TX_PARITY_bit_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    TX_PARITY_bit_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(TX_PARITY_bit_i_1_n_0),
        .Q(TX_PARITY_bit),
        .R(1'b0));
  IBUF UART_RX_IBUF_inst
       (.I(UART_RX),
        .O(UART_RX_IBUF));
  (* \PinAttr:D:HOLD_DETOUR  = "891" *) 
  FDRE #(
    .INIT(1'b0)) 
    UART_RX_d1_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(UART_RX_IBUF),
        .Q(UART_RX_d1),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    UART_RX_d2_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(UART_RX_d1),
        .Q(UART_RX_d2),
        .R(TX_DATA_SET_d_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    UART_RX_d3_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(1'b1),
        .D(UART_RX_d2),
        .Q(UART_RX_d3),
        .R(TX_DATA_SET_d_i_1_n_0));
  OBUF UART_TX_OBUF_inst
       (.I(UART_TX_OBUF),
        .O(UART_TX));
  (* OPT_MODIFIED = "RETARGET" *) 
  LUT2 #(
    .INIT(4'h8)) 
    UART_TX_f_i_1
       (.I0(TX_BIT_COUNTER_reg[0]),
        .I1(eqOp13_in),
        .O(TX_TIMING_SHIFT));
  LUT5 #(
    .INIT(32'hECFCFCEC)) 
    UART_TX_f_i_2
       (.I0(UART_TX_f_i_3_n_0),
        .I1(UART_TX_f_i_4_n_0),
        .I2(\TX_DATA_SHIFT_reg_n_0_[0] ),
        .I3(TX_BIT_COUNTER_reg[4]),
        .I4(TX_BIT_COUNTER_reg[1]),
        .O(UART_TX_f6_out));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    UART_TX_f_i_3
       (.I0(TX_BIT_COUNTER_reg[3]),
        .I1(TX_BIT_COUNTER_reg[7]),
        .I2(TX_BIT_COUNTER_reg[6]),
        .I3(TX_BIT_COUNTER_reg[5]),
        .I4(TX_BIT_COUNTER_reg[2]),
        .O(UART_TX_f_i_3_n_0));
  LUT6 #(
    .INIT(64'h00FF000000600000)) 
    UART_TX_f_i_4
       (.I0(TX_PARITY_bit),
        .I1(TX_PARITY_ODD_EVEN_d),
        .I2(TX_BIT_COUNTER_reg[1]),
        .I3(UART_TX_f_i_5_n_0),
        .I4(TX_BIT_COUNTER_reg[0]),
        .I5(TX_BIT_COUNTER_reg[2]),
        .O(UART_TX_f_i_4_n_0));
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    UART_TX_f_i_5
       (.I0(TX_BIT_COUNTER_reg[3]),
        .I1(TX_BIT_COUNTER_reg[7]),
        .I2(TX_BIT_COUNTER_reg[6]),
        .I3(TX_BIT_COUNTER_reg[5]),
        .I4(TX_BIT_COUNTER_reg[4]),
        .O(UART_TX_f_i_5_n_0));
  FDSE #(
    .INIT(1'b1)) 
    UART_TX_f_reg
       (.C(CLK20M_IBUF_bufg),
        .CE(TX_TIMING_SHIFT),
        .D(UART_TX_f6_out),
        .Q(UART_TX_OBUF),
        .S(TX_DATA_SET_d_i_1_n_0));
  IBUF nRESET_IBUF_inst
       (.I(nRESET),
        .O(nRESET_IBUF));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
