// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (win64) Build 6299465 Fri Nov 14 19:35:11 GMT 2025
// Date        : Wed Dec 17 04:59:27 2025
// Host        : intel_14700k running 64-bit major release  (build 9200)
// Command     : write_verilog -mode timesim -nolib -sdf_anno true -force -file
//               E:/XILINX_WORK/JapanLogicDesign/DDS_GENERATOR_MMCM/MAIN_001.sim/sim_1/impl/timing/xsim/TEST_BENCH_time_impl.v
// Design      : DDS_GENERATOR
// Purpose     : This verilog netlist is a timing simulation representation of the design and should not be modified or
//               synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device      : xc7s50csga324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING

(* ECO_CHECKSUM = "54f9dfdb" *) (* POWER_OPT_BRAM_CDC = "0" *) (* POWER_OPT_BRAM_SR_ADDR = "0" *) 
(* POWER_OPT_LOOPED_NET_PERCENTAGE = "0" *) 
(* NotValidForBitStream *)
(* \DesignAttr:ENABLE_NOC_NETLIST_VIEW  *) 
(* \DesignAttr:ENABLE_AIE_NETLIST_VIEW  *) 
module DDS_GENERATOR
   (nRESET,
    CLK20M,
    PHASE_DATA,
    WAVE_DATA_OUT);
  input nRESET;
  input CLK20M;
  input [19:0]PHASE_DATA;
  output [7:0]WAVE_DATA_OUT;

  (* IBUF_LOW_PWR *) wire CLK20M;
  wire CLK_MMCM;
  wire \PHASE_COUNT[0]_i_2_n_0 ;
  wire \PHASE_COUNT[0]_i_3_n_0 ;
  wire \PHASE_COUNT[0]_i_4_n_0 ;
  wire \PHASE_COUNT[0]_i_5_n_0 ;
  wire \PHASE_COUNT[12]_i_2_n_0 ;
  wire \PHASE_COUNT[12]_i_3_n_0 ;
  wire \PHASE_COUNT[12]_i_4_n_0 ;
  wire \PHASE_COUNT[12]_i_5_n_0 ;
  wire \PHASE_COUNT[16]_i_2_n_0 ;
  wire \PHASE_COUNT[16]_i_3_n_0 ;
  wire \PHASE_COUNT[16]_i_4_n_0 ;
  wire \PHASE_COUNT[16]_i_5_n_0 ;
  wire \PHASE_COUNT[4]_i_2_n_0 ;
  wire \PHASE_COUNT[4]_i_3_n_0 ;
  wire \PHASE_COUNT[4]_i_4_n_0 ;
  wire \PHASE_COUNT[4]_i_5_n_0 ;
  wire \PHASE_COUNT[8]_i_2_n_0 ;
  wire \PHASE_COUNT[8]_i_3_n_0 ;
  wire \PHASE_COUNT[8]_i_4_n_0 ;
  wire \PHASE_COUNT[8]_i_5_n_0 ;
  wire \PHASE_COUNT_reg[0]_i_1_n_0 ;
  wire \PHASE_COUNT_reg[0]_i_1_n_4 ;
  wire \PHASE_COUNT_reg[0]_i_1_n_5 ;
  wire \PHASE_COUNT_reg[0]_i_1_n_6 ;
  wire \PHASE_COUNT_reg[0]_i_1_n_7 ;
  wire \PHASE_COUNT_reg[12]_i_1_n_0 ;
  wire \PHASE_COUNT_reg[12]_i_1_n_4 ;
  wire \PHASE_COUNT_reg[12]_i_1_n_5 ;
  wire \PHASE_COUNT_reg[12]_i_1_n_6 ;
  wire \PHASE_COUNT_reg[12]_i_1_n_7 ;
  wire \PHASE_COUNT_reg[16]_i_1_n_0 ;
  wire \PHASE_COUNT_reg[16]_i_1_n_4 ;
  wire \PHASE_COUNT_reg[16]_i_1_n_5 ;
  wire \PHASE_COUNT_reg[16]_i_1_n_6 ;
  wire \PHASE_COUNT_reg[16]_i_1_n_7 ;
  wire \PHASE_COUNT_reg[20]_i_1_n_4 ;
  wire \PHASE_COUNT_reg[20]_i_1_n_5 ;
  wire \PHASE_COUNT_reg[20]_i_1_n_6 ;
  wire \PHASE_COUNT_reg[20]_i_1_n_7 ;
  wire \PHASE_COUNT_reg[4]_i_1_n_0 ;
  wire \PHASE_COUNT_reg[4]_i_1_n_4 ;
  wire \PHASE_COUNT_reg[4]_i_1_n_5 ;
  wire \PHASE_COUNT_reg[4]_i_1_n_6 ;
  wire \PHASE_COUNT_reg[4]_i_1_n_7 ;
  wire \PHASE_COUNT_reg[8]_i_1_n_0 ;
  wire \PHASE_COUNT_reg[8]_i_1_n_4 ;
  wire \PHASE_COUNT_reg[8]_i_1_n_5 ;
  wire \PHASE_COUNT_reg[8]_i_1_n_6 ;
  wire \PHASE_COUNT_reg[8]_i_1_n_7 ;
  wire \PHASE_COUNT_reg_n_0_[0] ;
  wire \PHASE_COUNT_reg_n_0_[10] ;
  wire \PHASE_COUNT_reg_n_0_[11] ;
  wire \PHASE_COUNT_reg_n_0_[12] ;
  wire \PHASE_COUNT_reg_n_0_[13] ;
  wire \PHASE_COUNT_reg_n_0_[14] ;
  wire \PHASE_COUNT_reg_n_0_[15] ;
  wire \PHASE_COUNT_reg_n_0_[1] ;
  wire \PHASE_COUNT_reg_n_0_[2] ;
  wire \PHASE_COUNT_reg_n_0_[3] ;
  wire \PHASE_COUNT_reg_n_0_[4] ;
  wire \PHASE_COUNT_reg_n_0_[5] ;
  wire \PHASE_COUNT_reg_n_0_[6] ;
  wire \PHASE_COUNT_reg_n_0_[7] ;
  wire \PHASE_COUNT_reg_n_0_[8] ;
  wire \PHASE_COUNT_reg_n_0_[9] ;
  wire [19:0]PHASE_DATA;
  wire [19:0]PHASE_DATA_IBUF;
  wire [19:0]PHASE_DATA_d1;
  wire [19:0]PHASE_DATA_d2;
  wire [7:0]RAM_ADD;
  wire [7:0]WAVE_DATA_OUT;
  wire [7:0]WAVE_DATA_OUT_OBUF;
  wire locked;
  wire m_WAVE_DATA_MEMORY_n_8;
  wire nRESET;
  wire nRESET_IBUF;
  wire [2:0]\NLW_PHASE_COUNT_reg[0]_i_1_CO_UNCONNECTED ;
  wire [2:0]\NLW_PHASE_COUNT_reg[12]_i_1_CO_UNCONNECTED ;
  wire [2:0]\NLW_PHASE_COUNT_reg[16]_i_1_CO_UNCONNECTED ;
  wire [3:0]\NLW_PHASE_COUNT_reg[20]_i_1_CO_UNCONNECTED ;
  wire [2:0]\NLW_PHASE_COUNT_reg[4]_i_1_CO_UNCONNECTED ;
  wire [2:0]\NLW_PHASE_COUNT_reg[8]_i_1_CO_UNCONNECTED ;

initial begin
 $sdf_annotate("TEST_BENCH_time_impl.sdf",,,,"tool_control");
end
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[0]_i_2 
       (.I0(PHASE_DATA_d2[3]),
        .I1(\PHASE_COUNT_reg_n_0_[3] ),
        .O(\PHASE_COUNT[0]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[0]_i_3 
       (.I0(PHASE_DATA_d2[2]),
        .I1(\PHASE_COUNT_reg_n_0_[2] ),
        .O(\PHASE_COUNT[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[0]_i_4 
       (.I0(PHASE_DATA_d2[1]),
        .I1(\PHASE_COUNT_reg_n_0_[1] ),
        .O(\PHASE_COUNT[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[0]_i_5 
       (.I0(PHASE_DATA_d2[0]),
        .I1(\PHASE_COUNT_reg_n_0_[0] ),
        .O(\PHASE_COUNT[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[12]_i_2 
       (.I0(PHASE_DATA_d2[15]),
        .I1(\PHASE_COUNT_reg_n_0_[15] ),
        .O(\PHASE_COUNT[12]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[12]_i_3 
       (.I0(PHASE_DATA_d2[14]),
        .I1(\PHASE_COUNT_reg_n_0_[14] ),
        .O(\PHASE_COUNT[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[12]_i_4 
       (.I0(PHASE_DATA_d2[13]),
        .I1(\PHASE_COUNT_reg_n_0_[13] ),
        .O(\PHASE_COUNT[12]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[12]_i_5 
       (.I0(PHASE_DATA_d2[12]),
        .I1(\PHASE_COUNT_reg_n_0_[12] ),
        .O(\PHASE_COUNT[12]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[16]_i_2 
       (.I0(PHASE_DATA_d2[19]),
        .I1(RAM_ADD[3]),
        .O(\PHASE_COUNT[16]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[16]_i_3 
       (.I0(PHASE_DATA_d2[18]),
        .I1(RAM_ADD[2]),
        .O(\PHASE_COUNT[16]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[16]_i_4 
       (.I0(PHASE_DATA_d2[17]),
        .I1(RAM_ADD[1]),
        .O(\PHASE_COUNT[16]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[16]_i_5 
       (.I0(PHASE_DATA_d2[16]),
        .I1(RAM_ADD[0]),
        .O(\PHASE_COUNT[16]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[4]_i_2 
       (.I0(PHASE_DATA_d2[7]),
        .I1(\PHASE_COUNT_reg_n_0_[7] ),
        .O(\PHASE_COUNT[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[4]_i_3 
       (.I0(PHASE_DATA_d2[6]),
        .I1(\PHASE_COUNT_reg_n_0_[6] ),
        .O(\PHASE_COUNT[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[4]_i_4 
       (.I0(PHASE_DATA_d2[5]),
        .I1(\PHASE_COUNT_reg_n_0_[5] ),
        .O(\PHASE_COUNT[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[4]_i_5 
       (.I0(PHASE_DATA_d2[4]),
        .I1(\PHASE_COUNT_reg_n_0_[4] ),
        .O(\PHASE_COUNT[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[8]_i_2 
       (.I0(PHASE_DATA_d2[11]),
        .I1(\PHASE_COUNT_reg_n_0_[11] ),
        .O(\PHASE_COUNT[8]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[8]_i_3 
       (.I0(PHASE_DATA_d2[10]),
        .I1(\PHASE_COUNT_reg_n_0_[10] ),
        .O(\PHASE_COUNT[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[8]_i_4 
       (.I0(PHASE_DATA_d2[9]),
        .I1(\PHASE_COUNT_reg_n_0_[9] ),
        .O(\PHASE_COUNT[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \PHASE_COUNT[8]_i_5 
       (.I0(PHASE_DATA_d2[8]),
        .I1(\PHASE_COUNT_reg_n_0_[8] ),
        .O(\PHASE_COUNT[8]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[0] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[0]_i_1_n_7 ),
        .Q(\PHASE_COUNT_reg_n_0_[0] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \PHASE_COUNT_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\PHASE_COUNT_reg[0]_i_1_n_0 ,\NLW_PHASE_COUNT_reg[0]_i_1_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI(PHASE_DATA_d2[3:0]),
        .O({\PHASE_COUNT_reg[0]_i_1_n_4 ,\PHASE_COUNT_reg[0]_i_1_n_5 ,\PHASE_COUNT_reg[0]_i_1_n_6 ,\PHASE_COUNT_reg[0]_i_1_n_7 }),
        .S({\PHASE_COUNT[0]_i_2_n_0 ,\PHASE_COUNT[0]_i_3_n_0 ,\PHASE_COUNT[0]_i_4_n_0 ,\PHASE_COUNT[0]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[10] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[8]_i_1_n_5 ),
        .Q(\PHASE_COUNT_reg_n_0_[10] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[11] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[8]_i_1_n_4 ),
        .Q(\PHASE_COUNT_reg_n_0_[11] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[12] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[12]_i_1_n_7 ),
        .Q(\PHASE_COUNT_reg_n_0_[12] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \PHASE_COUNT_reg[12]_i_1 
       (.CI(\PHASE_COUNT_reg[8]_i_1_n_0 ),
        .CO({\PHASE_COUNT_reg[12]_i_1_n_0 ,\NLW_PHASE_COUNT_reg[12]_i_1_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI(PHASE_DATA_d2[15:12]),
        .O({\PHASE_COUNT_reg[12]_i_1_n_4 ,\PHASE_COUNT_reg[12]_i_1_n_5 ,\PHASE_COUNT_reg[12]_i_1_n_6 ,\PHASE_COUNT_reg[12]_i_1_n_7 }),
        .S({\PHASE_COUNT[12]_i_2_n_0 ,\PHASE_COUNT[12]_i_3_n_0 ,\PHASE_COUNT[12]_i_4_n_0 ,\PHASE_COUNT[12]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[13] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[12]_i_1_n_6 ),
        .Q(\PHASE_COUNT_reg_n_0_[13] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[14] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[12]_i_1_n_5 ),
        .Q(\PHASE_COUNT_reg_n_0_[14] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[15] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[12]_i_1_n_4 ),
        .Q(\PHASE_COUNT_reg_n_0_[15] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[16] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[16]_i_1_n_7 ),
        .Q(RAM_ADD[0]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \PHASE_COUNT_reg[16]_i_1 
       (.CI(\PHASE_COUNT_reg[12]_i_1_n_0 ),
        .CO({\PHASE_COUNT_reg[16]_i_1_n_0 ,\NLW_PHASE_COUNT_reg[16]_i_1_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI(PHASE_DATA_d2[19:16]),
        .O({\PHASE_COUNT_reg[16]_i_1_n_4 ,\PHASE_COUNT_reg[16]_i_1_n_5 ,\PHASE_COUNT_reg[16]_i_1_n_6 ,\PHASE_COUNT_reg[16]_i_1_n_7 }),
        .S({\PHASE_COUNT[16]_i_2_n_0 ,\PHASE_COUNT[16]_i_3_n_0 ,\PHASE_COUNT[16]_i_4_n_0 ,\PHASE_COUNT[16]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[17] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[16]_i_1_n_6 ),
        .Q(RAM_ADD[1]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[18] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[16]_i_1_n_5 ),
        .Q(RAM_ADD[2]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[19] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[16]_i_1_n_4 ),
        .Q(RAM_ADD[3]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[1] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[0]_i_1_n_6 ),
        .Q(\PHASE_COUNT_reg_n_0_[1] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[20] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[20]_i_1_n_7 ),
        .Q(RAM_ADD[4]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \PHASE_COUNT_reg[20]_i_1 
       (.CI(\PHASE_COUNT_reg[16]_i_1_n_0 ),
        .CO(\NLW_PHASE_COUNT_reg[20]_i_1_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\PHASE_COUNT_reg[20]_i_1_n_4 ,\PHASE_COUNT_reg[20]_i_1_n_5 ,\PHASE_COUNT_reg[20]_i_1_n_6 ,\PHASE_COUNT_reg[20]_i_1_n_7 }),
        .S(RAM_ADD[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[21] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[20]_i_1_n_6 ),
        .Q(RAM_ADD[5]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[22] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[20]_i_1_n_5 ),
        .Q(RAM_ADD[6]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[23] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[20]_i_1_n_4 ),
        .Q(RAM_ADD[7]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[2] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[0]_i_1_n_5 ),
        .Q(\PHASE_COUNT_reg_n_0_[2] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[3] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[0]_i_1_n_4 ),
        .Q(\PHASE_COUNT_reg_n_0_[3] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[4] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[4]_i_1_n_7 ),
        .Q(\PHASE_COUNT_reg_n_0_[4] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \PHASE_COUNT_reg[4]_i_1 
       (.CI(\PHASE_COUNT_reg[0]_i_1_n_0 ),
        .CO({\PHASE_COUNT_reg[4]_i_1_n_0 ,\NLW_PHASE_COUNT_reg[4]_i_1_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI(PHASE_DATA_d2[7:4]),
        .O({\PHASE_COUNT_reg[4]_i_1_n_4 ,\PHASE_COUNT_reg[4]_i_1_n_5 ,\PHASE_COUNT_reg[4]_i_1_n_6 ,\PHASE_COUNT_reg[4]_i_1_n_7 }),
        .S({\PHASE_COUNT[4]_i_2_n_0 ,\PHASE_COUNT[4]_i_3_n_0 ,\PHASE_COUNT[4]_i_4_n_0 ,\PHASE_COUNT[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[5] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[4]_i_1_n_6 ),
        .Q(\PHASE_COUNT_reg_n_0_[5] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[6] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[4]_i_1_n_5 ),
        .Q(\PHASE_COUNT_reg_n_0_[6] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[7] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[4]_i_1_n_4 ),
        .Q(\PHASE_COUNT_reg_n_0_[7] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[8] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[8]_i_1_n_7 ),
        .Q(\PHASE_COUNT_reg_n_0_[8] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \PHASE_COUNT_reg[8]_i_1 
       (.CI(\PHASE_COUNT_reg[4]_i_1_n_0 ),
        .CO({\PHASE_COUNT_reg[8]_i_1_n_0 ,\NLW_PHASE_COUNT_reg[8]_i_1_CO_UNCONNECTED [2:0]}),
        .CYINIT(1'b0),
        .DI(PHASE_DATA_d2[11:8]),
        .O({\PHASE_COUNT_reg[8]_i_1_n_4 ,\PHASE_COUNT_reg[8]_i_1_n_5 ,\PHASE_COUNT_reg[8]_i_1_n_6 ,\PHASE_COUNT_reg[8]_i_1_n_7 }),
        .S({\PHASE_COUNT[8]_i_2_n_0 ,\PHASE_COUNT[8]_i_3_n_0 ,\PHASE_COUNT[8]_i_4_n_0 ,\PHASE_COUNT[8]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_COUNT_reg[9] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(\PHASE_COUNT_reg[8]_i_1_n_6 ),
        .Q(\PHASE_COUNT_reg_n_0_[9] ),
        .R(m_WAVE_DATA_MEMORY_n_8));
  IBUF \PHASE_DATA_IBUF[0]_inst 
       (.I(PHASE_DATA[0]),
        .O(PHASE_DATA_IBUF[0]));
  IBUF \PHASE_DATA_IBUF[10]_inst 
       (.I(PHASE_DATA[10]),
        .O(PHASE_DATA_IBUF[10]));
  IBUF \PHASE_DATA_IBUF[11]_inst 
       (.I(PHASE_DATA[11]),
        .O(PHASE_DATA_IBUF[11]));
  IBUF \PHASE_DATA_IBUF[12]_inst 
       (.I(PHASE_DATA[12]),
        .O(PHASE_DATA_IBUF[12]));
  IBUF \PHASE_DATA_IBUF[13]_inst 
       (.I(PHASE_DATA[13]),
        .O(PHASE_DATA_IBUF[13]));
  IBUF \PHASE_DATA_IBUF[14]_inst 
       (.I(PHASE_DATA[14]),
        .O(PHASE_DATA_IBUF[14]));
  IBUF \PHASE_DATA_IBUF[15]_inst 
       (.I(PHASE_DATA[15]),
        .O(PHASE_DATA_IBUF[15]));
  IBUF \PHASE_DATA_IBUF[16]_inst 
       (.I(PHASE_DATA[16]),
        .O(PHASE_DATA_IBUF[16]));
  IBUF \PHASE_DATA_IBUF[17]_inst 
       (.I(PHASE_DATA[17]),
        .O(PHASE_DATA_IBUF[17]));
  IBUF \PHASE_DATA_IBUF[18]_inst 
       (.I(PHASE_DATA[18]),
        .O(PHASE_DATA_IBUF[18]));
  IBUF \PHASE_DATA_IBUF[19]_inst 
       (.I(PHASE_DATA[19]),
        .O(PHASE_DATA_IBUF[19]));
  IBUF \PHASE_DATA_IBUF[1]_inst 
       (.I(PHASE_DATA[1]),
        .O(PHASE_DATA_IBUF[1]));
  IBUF \PHASE_DATA_IBUF[2]_inst 
       (.I(PHASE_DATA[2]),
        .O(PHASE_DATA_IBUF[2]));
  IBUF \PHASE_DATA_IBUF[3]_inst 
       (.I(PHASE_DATA[3]),
        .O(PHASE_DATA_IBUF[3]));
  IBUF \PHASE_DATA_IBUF[4]_inst 
       (.I(PHASE_DATA[4]),
        .O(PHASE_DATA_IBUF[4]));
  IBUF \PHASE_DATA_IBUF[5]_inst 
       (.I(PHASE_DATA[5]),
        .O(PHASE_DATA_IBUF[5]));
  IBUF \PHASE_DATA_IBUF[6]_inst 
       (.I(PHASE_DATA[6]),
        .O(PHASE_DATA_IBUF[6]));
  IBUF \PHASE_DATA_IBUF[7]_inst 
       (.I(PHASE_DATA[7]),
        .O(PHASE_DATA_IBUF[7]));
  IBUF \PHASE_DATA_IBUF[8]_inst 
       (.I(PHASE_DATA[8]),
        .O(PHASE_DATA_IBUF[8]));
  IBUF \PHASE_DATA_IBUF[9]_inst 
       (.I(PHASE_DATA[9]),
        .O(PHASE_DATA_IBUF[9]));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[0] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[0]),
        .Q(PHASE_DATA_d1[0]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[10] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[10]),
        .Q(PHASE_DATA_d1[10]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[11] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[11]),
        .Q(PHASE_DATA_d1[11]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[12] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[12]),
        .Q(PHASE_DATA_d1[12]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[13] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[13]),
        .Q(PHASE_DATA_d1[13]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[14] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[14]),
        .Q(PHASE_DATA_d1[14]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[15] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[15]),
        .Q(PHASE_DATA_d1[15]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[16] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[16]),
        .Q(PHASE_DATA_d1[16]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[17] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[17]),
        .Q(PHASE_DATA_d1[17]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[18] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[18]),
        .Q(PHASE_DATA_d1[18]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[19] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[19]),
        .Q(PHASE_DATA_d1[19]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[1] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[1]),
        .Q(PHASE_DATA_d1[1]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[2] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[2]),
        .Q(PHASE_DATA_d1[2]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[3] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[3]),
        .Q(PHASE_DATA_d1[3]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[4] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[4]),
        .Q(PHASE_DATA_d1[4]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[5] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[5]),
        .Q(PHASE_DATA_d1[5]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[6] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[6]),
        .Q(PHASE_DATA_d1[6]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[7] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[7]),
        .Q(PHASE_DATA_d1[7]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[8] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[8]),
        .Q(PHASE_DATA_d1[8]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d1_reg[9] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_IBUF[9]),
        .Q(PHASE_DATA_d1[9]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[0] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[0]),
        .Q(PHASE_DATA_d2[0]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[10] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[10]),
        .Q(PHASE_DATA_d2[10]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[11] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[11]),
        .Q(PHASE_DATA_d2[11]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[12] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[12]),
        .Q(PHASE_DATA_d2[12]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[13] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[13]),
        .Q(PHASE_DATA_d2[13]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[14] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[14]),
        .Q(PHASE_DATA_d2[14]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[15] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[15]),
        .Q(PHASE_DATA_d2[15]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[16] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[16]),
        .Q(PHASE_DATA_d2[16]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[17] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[17]),
        .Q(PHASE_DATA_d2[17]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[18] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[18]),
        .Q(PHASE_DATA_d2[18]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[19] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[19]),
        .Q(PHASE_DATA_d2[19]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[1] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[1]),
        .Q(PHASE_DATA_d2[1]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[2] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[2]),
        .Q(PHASE_DATA_d2[2]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[3] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[3]),
        .Q(PHASE_DATA_d2[3]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[4] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[4]),
        .Q(PHASE_DATA_d2[4]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[5] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[5]),
        .Q(PHASE_DATA_d2[5]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[6] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[6]),
        .Q(PHASE_DATA_d2[6]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[7] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[7]),
        .Q(PHASE_DATA_d2[7]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[8] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[8]),
        .Q(PHASE_DATA_d2[8]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  FDRE #(
    .INIT(1'b0)) 
    \PHASE_DATA_d2_reg[9] 
       (.C(CLK_MMCM),
        .CE(1'b1),
        .D(PHASE_DATA_d1[9]),
        .Q(PHASE_DATA_d2[9]),
        .R(m_WAVE_DATA_MEMORY_n_8));
  OBUF \WAVE_DATA_OUT_OBUF[0]_inst 
       (.I(WAVE_DATA_OUT_OBUF[0]),
        .O(WAVE_DATA_OUT[0]));
  OBUF \WAVE_DATA_OUT_OBUF[1]_inst 
       (.I(WAVE_DATA_OUT_OBUF[1]),
        .O(WAVE_DATA_OUT[1]));
  OBUF \WAVE_DATA_OUT_OBUF[2]_inst 
       (.I(WAVE_DATA_OUT_OBUF[2]),
        .O(WAVE_DATA_OUT[2]));
  OBUF \WAVE_DATA_OUT_OBUF[3]_inst 
       (.I(WAVE_DATA_OUT_OBUF[3]),
        .O(WAVE_DATA_OUT[3]));
  OBUF \WAVE_DATA_OUT_OBUF[4]_inst 
       (.I(WAVE_DATA_OUT_OBUF[4]),
        .O(WAVE_DATA_OUT[4]));
  OBUF \WAVE_DATA_OUT_OBUF[5]_inst 
       (.I(WAVE_DATA_OUT_OBUF[5]),
        .O(WAVE_DATA_OUT[5]));
  OBUF \WAVE_DATA_OUT_OBUF[6]_inst 
       (.I(WAVE_DATA_OUT_OBUF[6]),
        .O(WAVE_DATA_OUT[6]));
  OBUF \WAVE_DATA_OUT_OBUF[7]_inst 
       (.I(WAVE_DATA_OUT_OBUF[7]),
        .O(WAVE_DATA_OUT[7]));
  WAVE_DATA_MEMORY m_WAVE_DATA_MEMORY
       (.DOADO(WAVE_DATA_OUT_OBUF),
        .clear(m_WAVE_DATA_MEMORY_n_8),
        .clk_out1(CLK_MMCM),
        .locked(locked),
        .nRESET_IBUF(nRESET_IBUF),
        .out(RAM_ADD));
  (* IMPORTED_FROM = "e:/XILINX_WORK/JapanLogicDesign/DDS_GENERATOR_MMCM/MAIN_001.gen/sources_1/ip/clk_wiz_0_1/clk_wiz_0.dcp" *) 
  (* IMPORTED_TYPE = "CHECKPOINT" *) 
  (* IS_IMPORTED *) 
  (* syn_black_box = "TRUE" *) 
  clk_wiz_0 m_clk_wiz_0
       (.clk_in1(CLK20M),
        .clk_out1(CLK_MMCM),
        .locked(locked),
        .reset(nRESET_IBUF));
  IBUF nRESET_IBUF_inst
       (.I(nRESET),
        .O(nRESET_IBUF));
endmodule

module WAVE_DATA_MEMORY
   (DOADO,
    clear,
    clk_out1,
    out,
    locked,
    nRESET_IBUF);
  output [7:0]DOADO;
  output clear;
  input clk_out1;
  input [7:0]out;
  input locked;
  input nRESET_IBUF;

  wire [7:0]DOADO;
  wire clear;
  wire clk_out1;
  wire locked;
  wire nRESET_IBUF;
  wire [7:0]out;
  wire [15:8]NLW_SRAM_ARRAY_reg_DOADO_UNCONNECTED;
  wire [15:0]NLW_SRAM_ARRAY_reg_DOBDO_UNCONNECTED;
  wire [1:0]NLW_SRAM_ARRAY_reg_DOPADOP_UNCONNECTED;
  wire [1:0]NLW_SRAM_ARRAY_reg_DOPBDOP_UNCONNECTED;

  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p0_d8" *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "2048" *) 
  (* RTL_RAM_NAME = "m_WAVE_DATA_MEMORY/SRAM_ARRAY_reg" *) 
  (* RTL_RAM_STYLE = "auto" *) 
  (* RTL_RAM_TYPE = "RAM_SP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "1023" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "7" *) 
  RAMB18E1 #(
    .DOA_REG(1),
    .DOB_REG(0),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h00AD00AA00A700A500A2009E009B009800950092008F008C0089008600830080),
    .INIT_01(256'h00D700D500D300D000CE00CB00C900C600C400C100BE00BC00B900B600B300B0),
    .INIT_02(256'h00F400F300F100F000EE00ED00EB00EA00E800E600E400E200E000DE00DC00DA),
    .INIT_03(256'h00FF00FF00FF00FE00FE00FE00FD00FD00FC00FB00FA00FA00F900F800F600F5),
    .INIT_04(256'h00F600F800F900FA00FA00FB00FC00FD00FD00FE00FE00FE00FF00FF00FF00FF),
    .INIT_05(256'h00DC00DE00E000E200E400E600E800EA00EB00ED00EE00F000F100F300F400F5),
    .INIT_06(256'h00B300B600B900BC00BE00C100C400C600C900CB00CE00D000D300D500D700DA),
    .INIT_07(256'h008300860089008C008F009200950098009B009E00A200A500A700AA00AD00B0),
    .INIT_08(256'h005200550058005A005D006100640067006A006D0070007300760079007C0080),
    .INIT_09(256'h0028002A002C002F0031003400360039003B003E0041004300460049004C004F),
    .INIT_0A(256'h000B000C000E000F001100120014001500170019001B001D001F002100230025),
    .INIT_0B(256'h000000000000000100010001000200020003000400050005000600070009000A),
    .INIT_0C(256'h0009000700060005000500040003000200020001000100010000000000000000),
    .INIT_0D(256'h00230021001F001D001B001900170015001400120011000F000E000C000B000A),
    .INIT_0E(256'h004C0049004600430041003E003B0039003600340031002F002C002A00280025),
    .INIT_0F(256'h007C0079007600730070006D006A006700640061005D005A005800550052004F),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .INIT_FILE("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(0)) 
    SRAM_ARRAY_reg
       (.ADDRARDADDR({1'b0,1'b0,out,1'b0,1'b0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CLKARDCLK(clk_out1),
        .CLKBWRCLK(1'b0),
        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DIPADIP({1'b0,1'b0}),
        .DIPBDIP({1'b1,1'b1}),
        .DOADO({NLW_SRAM_ARRAY_reg_DOADO_UNCONNECTED[15:8],DOADO}),
        .DOBDO(NLW_SRAM_ARRAY_reg_DOBDO_UNCONNECTED[15:0]),
        .DOPADOP(NLW_SRAM_ARRAY_reg_DOPADOP_UNCONNECTED[1:0]),
        .DOPBDOP(NLW_SRAM_ARRAY_reg_DOPBDOP_UNCONNECTED[1:0]),
        .ENARDEN(1'b1),
        .ENBWREN(1'b0),
        .REGCEAREGCE(1'b1),
        .REGCEB(1'b0),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(clear),
        .RSTREGB(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0}));
  LUT2 #(
    .INIT(4'h7)) 
    SRAM_ARRAY_reg_i_1
       (.I0(locked),
        .I1(nRESET_IBUF),
        .O(clear));
endmodule

module clk_wiz_0
   (clk_out1,
    reset,
    locked,
    clk_in1);
  output clk_out1;
  input reset;
  output locked;
  input clk_in1;

  wire clk_in1;
  wire clk_out1;
  wire locked;
  wire reset;

  clk_wiz_0_clk_wiz inst
       (.clk_in1(clk_in1),
        .clk_out1(clk_out1),
        .locked(locked),
        .reset(reset));
endmodule

module clk_wiz_0_clk_wiz
   (clk_out1,
    reset,
    locked,
    clk_in1);
  output clk_out1;
  input reset;
  output locked;
  input clk_in1;

  wire clk_in1;
  wire clk_in1_clk_wiz_0;
  wire clk_out1;
  wire clk_out1_clk_wiz_0;
  wire clkfbout_buf_clk_wiz_0;
  wire clkfbout_clk_wiz_0;
  wire locked;
  wire reset;
  wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
  wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
  wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
  wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
  wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG clkf_buf
       (.I(clkfbout_clk_wiz_0),
        .O(clkfbout_buf_clk_wiz_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  (* IBUF_DELAY_VALUE = "0" *) 
  (* IFD_DELAY_VALUE = "AUTO" *) 
  IBUF #(
    .IOSTANDARD("DEFAULT")) 
    clkin1_ibufg
       (.I(clk_in1),
        .O(clk_in1_clk_wiz_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG clkout1_buf
       (.I(clk_out1_clk_wiz_0),
        .O(clk_out1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "RETARGET" *) 
  MMCME2_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT_F(48.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(50.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(18.750000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("FALSE"),
    .CLKOUT1_DIVIDE(1),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(1),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(0.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(1),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(1),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("ZHOLD"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PSEN_INVERTED(1'b0),
    .IS_PSINCDEC_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b1),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .SS_EN("FALSE"),
    .SS_MODE("CENTER_HIGH"),
    .SS_MOD_PERIOD(10000),
    .STARTUP_WAIT("FALSE")) 
    mmcm_adv_inst
       (.CLKFBIN(clkfbout_buf_clk_wiz_0),
        .CLKFBOUT(clkfbout_clk_wiz_0),
        .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
        .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
        .CLKIN1(clk_in1_clk_wiz_0),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
        .CLKOUT0(clk_out1_clk_wiz_0),
        .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
        .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
        .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
        .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
        .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
        .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
        .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
        .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
        .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
        .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
        .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
        .DWE(1'b0),
        .LOCKED(locked),
        .PSCLK(1'b0),
        .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
