@echo off
REM ****************************************************************************
REM Vivado (TM) v2025.2 (64-bit)
REM
REM Filename    : compile.bat
REM Simulator   : AMD Vivado Simulator
REM Description : Script for compiling the simulation design source files
REM
REM Generated by Vivado on Wed Dec 17 05:43:11 +0900 2025
REM SW Build 6299465 on Fri Nov 14 19:35:11 GMT 2025
REM
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
REM Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
REM
REM usage: compile.bat
REM
REM ****************************************************************************
set SIM_VER_XSIM=
set GCC_VER_XSIM=9.3.0

REM compile Verilog/System Verilog design sources
echo "xvlog --incr --relax -prj TEST_BENCH_vlog.prj"
call xvlog  --incr --relax -prj TEST_BENCH_vlog.prj -log xvlog.log
call type xvlog.log > compile.log
REM compile VHDL design sources
echo "xvhdl --incr --relax -prj TEST_BENCH_vhdl.prj"
call xvhdl  --incr --relax -prj TEST_BENCH_vhdl.prj -log xvhdl.log
call type xvhdl.log >> compile.log
if "%errorlevel%"=="1" goto END
if "%errorlevel%"=="0" goto SUCCESS
:END
exit 1
:SUCCESS
exit 0
